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Technical Data Advance Information
MSC8102/D Rev. 2, 4/2003 Quad Core 16-Bit Digital Signal Processor
SC140 Extended Core MQBus
SC140 Extended Core 128 SQBus
SC140 Extended Core
SC140 Extended Core
Boot ROM
128 64 IP Master
Local Bus
The raw processing power of this highly integrated system-ona-chip device enables developers to create next generation networking products that offer tremendous channel densities, while maintaining system flexibility, scalability, and upgradeability. The MSC8102 is offered in two core speed levels: 250 and 275 MHz.
M2 RAM
32 Timers Memory Controller* UART 4 TDMs IPBus GPIO GIC 32 8 Hardware Semaphores Direct Slave Interface (DSI) Memory Controller* DSI Port 32/64 60x-compatible System Bus 32/64 GPIO Pins Interrupts RS-232
PLL/Clock
PLL
JTAG Port
JTAG
64 System Interface DMA
Internal Local Bus Bridge SIU Registers 64
Internal System Bus
*There is a single memory controller that controls access to both the local bus and the system bus.
Figure 1. MSC8102 Block Diagram The MSC8102 is a highly integrated system-ona-chip that combines four StarCore SC140 extended cores with an RS-232 serial interface, four time-division multiplexed (TDM) serial interfaces, thirty-two general-purpose timers, a flexible system interface unit (SIU), and a multi-channel DMA engine. The four extended cores can deliver a total 4400 DSP MMACS performance at 275 MHz. Each core has four arithmetic logic units (ALUs), internal memory, a write buffer, and two interrupt controllers. The MSC8102 targets high-bandwidth highly computational DSP applications and is optimized for wireless transcoding and packet telephony as well as high-bandwidth base station applications. The MSC8102 delivers enhanced performance while maintaining low power dissipation and greatly reduces system cost.
Note: This document contains information on a new product. Specifications and information herein are subject to change without notice.
Table of Contents
Features .............................................................................................................................................................. iv Product Documentation.................................................................................................................................... viii
Chapter 1
Signal/ Connection Description
1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 Power Signals................................................................................................................................................... 1-3 Clock Signals ................................................................................................................................................... 1-3 Reset and Configuration Signals...................................................................................................................... 1-4 Direct Slave Interface, System Bus, and Interrupt Signals .............................................................................. 1-4 Memory Controller Signals............................................................................................................................ 1-12 GPIO, TDM, UART, and Timer Signals ........................................................................................................ 1-14 EOnCE Event and JTAG Test Access Port Signals ....................................................................................... 1-22 Reserved Signals ............................................................................................................................................ 1-22 Introduction ...................................................................................................................................................... 2-1 Maximum Ratings............................................................................................................................................ 2-2 Recommended Operating Conditions .............................................................................................................. 2-3 Thermal Characteristics ................................................................................................................................... 2-3 DC Electrical Characteristics ........................................................................................................................... 2-4 AC Timings ...................................................................................................................................................... 2-5 Pinout and Package Information ...................................................................................................................... 3-1 FC-CBGA (HCTE) Package Description ........................................................................................................ 3-1 FC-CBGA (HCTE) Package Mechanical Drawing ....................................................................................... 3-34 FC-PBGA Package Mechanical Drawing...................................................................................................... 3-35 Thermal Design Considerations....................................................................................................................... 4-1 Power Supply Design Considerations.............................................................................................................. 4-1 Connectivity Guidelines................................................................................................................................... 4-2 Power Considerations....................................................................................................................................... 4-3 Layout Practices ............................................................................................................................................... 4-4
Chapter 2
Specifications
2.1 2.2 2.3 2.4 2.5 2.6
Chapter 3
Packaging
3.1 3.2 3.3 3.4
Chapter 4
Design Considerations
4.1 4.2 4.3 4.4 4.5
Data Sheet Conventions
OVERBAR "asserted" "deasserted"
Examples:
Used to indicate a signal that is active when pulled low (For example, the RESET pin is active when low.) Means that a high true (active high) signal is high or that a low true (active low) signal is low Means that a high true (active high) signal is low or that a low true (active low) signal is high
Signal/Symbol PIN PIN PIN PIN Logic State True False True False Signal State Asserted Deasserted Asserted Deasserted Voltage VIL/VOL VIH/VOH VIH/VOH VIL/VOL
Note: Values for V IL, VOL, VIH , and VOH are defined by individual product specifications.
ii
Program Sequencer SC140 Core JTAG
Address Register File Address ALU EOnCETM
Data ALU Register File Data ALU
Power Management
SC140 Core EOnCETM Xa Xb P 64 64 128
M1 RAM
Instruction Cache QBus 128 PIC IRQs LIC QBus Bank 1 QBus Bank 3
QBC
QBus Interface
IRQs
MQBus SQBus Local Bus
128 128 64
Notes: 1. The arrows show the data transfer direction. 2. The QBus interface includes a bus switch, write buffer, fetch unit, and a control unit that defines four QBus banks. In addition, the QBC handles internal memory contentions.
Figure 2. SC140 Extended Core Block Diagram
iii
Features
* Four high-performance StarCore SC140 Digital Signal Processor (DSP) extended cores delivering up to 4400 MMACS using 16 ALUs running at up to 275 MHz, delivering a performance equivalent to a single SC140 core running at 1.1 GHz * Each extended core includes: -- SC140 core processor. -- Local 224 KB memory space (M1) accessed by the SC140 core with no wait states and atomic access. -- 16 KB, 16-way instruction cache (ICache). -- Programmable interrupt controller (PIC). -- Local interrupt controller (LIC). * Each SC140 core provides the following: -- Up to 1100 million multiply-accumulates per second (MMACS) using an internal 275 MHz clock at 1.6 V. A multiply-accumulate operation includes a multiply-add instruction with the associated data move and pointer update. -- 4 ALUs per SC140 core. -- 16 data registers, 40 bits each. -- 27 address registers, 32 bits each. -- Hardware support for fractional and integer data types. -- Very rich 16-bit wide orthogonal instruction set. -- Up to six instructions executed in a single clock cycle. -- Variable-length execution set (VLES) that can be optimized for code density and performance. -- IEEE 1149.1 JTAG port. -- Enhanced on-device emulation (EOnCE) module with real-time debugging capabilities. * Large internal memory spaces (1.440 MB total). -- 224 KB of M1 memory per core (896 KB total). -- 16 KB of ICache per core (64 KB total). -- 476 KB shared memory (M2) operating at the core frequency, accessible from all four SC140 cores via the MQBus, and accessible from the local bus. -- 4 KB boot ROM accessible from all four SC140 cores via the MQBus. * Internal PLL for generating up to 275 MHz clock for the SC140 cores and up to 91.67 MHz for the 60x-compatible system bus, the local bus and other modules. PLL values are determined at reset based on configuration signal values. * Very flexible System Interface Unit (SIU) with a memory controller to support a 32/64-bit wide 60x-compatible system bus to access memory and memory-mapped devices: -- Reset controller. -- Real-time clock register. -- Periodic interrupt timer (PIT). -- Hardware bus monitors for the 60x-compatible system bus and local bus. -- Software watchdog timer function. * Flexible eight-bank memory controller: -- Three user-programmable machines (UPMs), general-purpose chip-select machine (GPCM), and a page-mode SDRAM machine. -- Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, FLASH and other user-definable peripherals. -- Byte enables for either 64-bit or 32-bit bus width mode. -- Eight external memory banks (banks 0-7). Two additional memory banks control IPBus peripherals and internal memories (banks 9, 11). Each bank has the following features: iv
*
*
*
*
32-bit address decoding with programmable mask. Variable block sizes (32 KB to 4 GB). Selectable memory controller machine. Two types of data errors check/correction (on 60x-compatible system bus only): Normal odd/even parity and Read-modify-write (RMW) odd/even parity for single accesses. Write-protection capability. Control signal generation machine selection on a per-bank basis. Flexible chip-select assignment between the 60x-compatible system bus and local bus. Support for internal or external masters on the 60x-compatible system bus. Data buffer controls activated on a per-bank basis. Atomic operation. RMW data parity check (on 60x-compatible system bus only). Extensive external memory-controller/bus-slave support. Parity byte select signal, which enables a fast, glueless connection to RMW-parity devices (on 60x-compatible system bus only). Data pipeline to reduce data set-up time for synchronous devices. Direct Slave Interface (DSI) that provides a 32/64-bit wide slave host interface. It is part of a dual-system bus architecture shared with the external system bus. The dual architecture allows the DSI data bus to be 32 or 64 bits wide and the system data bus to be 64 or 32 bits wide, respectively. It operates only as a slave device under the control of an external host processor. Multi-channel DMA controller: -- 16 time-multiplexed unidirectional channels with infrastructure of 32 channels. -- Services up to four external peripherals. -- Supports DONE or DRACK protocol on two external peripherals. -- Each channel group services 16 internal requests generated by eight internal FIFOs. Each FIFO generates: a watermark request to indicate that the FIFO contains data for the DMA to empty and write to the destination a hungry request to indicate that the FIFO can accept more data. -- Priority-based time-multiplexing between channels using 16 internal priority levels -- A flexible channel configuration: All channels support all features. All channels connect to the 60x-compatible system bus or local bus. -- Flyby transfers in which a single data access is transferred directly from the source to the destination without using a DMA FIFO. External interfaces and control modules managed on the internal peripheral bus (IPBus) by an IP master device, including: -- Four time-division multiplexing (TDM) modules, each supporting up to 64 channels (256 channels total) -- RS-232 interface/universal asynchronous receiver/transmitter (UART) -- Two 16-timer modules (32 timers total) -- Eight hardware semaphore registers used by external hosts to control shared resources and ensure data coherency -- Thirty-two general-purpose input/output (GPIO) signals -- Global interrupt controller (GIC) to handle external interrupt functions (input and output) Up to four independent TDM modules, each with the following features: -- Either totally independent receive and transmit, each having one data line, one clock line, and one frame sync line or four data lines, one clock and one frame sync that are shared between the transmit and receive. -- Glueless interface to E1/T1 frames and MVIP, SCAS, and H.110 buses.
v
-- Hardware A-law/-law conversion -- Up to 50 Mbps per TDM (50 MHz bit clock if one data line is used, 25 MHz if two data lines are used, 12.5 MHz if four data lines are used). -- Up to 256 channels. -- Up to 16 MB per channel buffer (granularity 8 bytes), where A/ law buffer size is double (granularity 16 byte) -- Receive buffers share one global write offset pointer that is written to the same offset relative to their start address. -- Transmit buffers share one global read offset pointer that is read from the same offset relative to their start address. -- All channels share the same word size. -- Two programmable receive and two programmable transmit threshold levels with interrupt generation that can be used, for example, to implement double buffering. -- Each channel can be programmed to be active or inactive. -- 2-, 4-, 8-, or 16-bit channels are stored in the internal memory as 2-, 4-, 8-, or 16-bit channels, respectively. -- The TDM Transmitter Sync Signal (TxTSYN) can be configured as either input or output. -- Frame Sync and Data signals can be programmed to be sampled either on the rising edge or on the falling edge of the clock. -- Frame sync can be programmed as active low or active high. -- Selectable delay (0-3 bits) between the Frame Sync signal and the beginning of the frame. -- MSB or LSB first support. * UART -- Two signals for transmit data and receive data. -- No clock, asynchronous mode. -- Can be serviced either by the SC140 DSP cores or an external host on the 60x-compatible system bus or on the DSI. -- Full-duplex operation. -- Standard mark/space non-return-to-zero (NRZ) format. -- 13-bit baud rate selection. -- Programmable 8-bit or 9-bit data format. -- Separately enabled transmitter and receiver. -- Programmable transmitter output polarity. -- Two receiver wakeup methods: Idle line wakeup. Address mark wakeup. -- Separate receiver and transmitter interrupt requests. -- Eight flags, the first five can generate interrupt request: Transmitter empty. Transmission complete. Receiver full. Idle receiver input. Receiver overrun. Noise error. Framing error. Parity error. -- Receiver framing error detection. -- Hardware parity checking. -- 1/16 bit-time noise detection. -- Maximum bit rate 6.25 Mbps. vi
-- Single-wire and loop operations. * Timers -- Two modules of 16 timers each. -- Each timer has the following features: Cyclic or one-shot. Input clock polarity control. Interrupt request when counting reaches a programmed threshold. Pulse or level interrupts. Dynamically updated programmed threshold. Read counter any time. -- Watchdog mode for the timers that connect to the device. * Hardware semaphores. Eight coded hardware semaphores, locked by simple write access without need for read-modify-write mechanism. * General-Purpose I/O (GPIO) port: -- 32 bidirectional signal lines that either serve the peripherals or act as programmable I/O ports. -- Each port can be programmed separately to serve up to two dedicated peripherals, and each port supports open-drain output mode. * Global Interrupt Controller (GIC): -- Consolidation of chip maskable interrupt and non-maskable interrupt sources and routing to INT_OUT, NMI_OUT, and to the cores. -- Generation of 32 virtual interrupts (eight to each SC140 core) by a simple write access. -- Generation of virtual NMI (one to each SC140 core) by a simple write access. * Software support, with support from industry-leading third parties: -- Real-Time Operating Systems (RTOS): Fully supports MSC8102 device architecture (multi-core, memory hierarchy, ICache, timers, DMA, interrupts, peripherals). - High-performance and deterministic, delivering predictive response time. - Optimized to provide low interrupt latency with high data throughput. - Preemptive and priority-based multitasking. - Fully interrupt/event driven. - Small memory footprint. - Comprehensive set of APIs. - Fully supports MSC8102 DMA, interrupts, and timer schemes. Multi-core support: - Enables use of one instance of kernel code all four SC140 cores. - Dynamic and static memory allocation from local memory (M1) and shared memory (M2). Distributed system support, enables transparent inter-task communications between tasks running inside the SC140 cores and the other tasks running on devices on the board or remote devices in the network - Messaging mechanism between tasks using mailboxes and semaphores. - Networking support; data transfer between tasks running inside and outside the device using networking protocols. - Includes integrated device drivers for such peripherals as TDM, UART, and external buses. Additional features: - Incorporates task debugging utilities integrated with compilers and vendors. - Board support package (BSP) for MSC8102ADS. -- Integrated Development Environment (IDE):
vii
C/C++ compiler with in-line assembly. Enables the developer to generate highly optimized DSP code. It translates code written in C/C++ into parallel fetch sets and maintains high code density. Librarian. Enables the user to create libraries for modularity. C libraries. A collection of C/C++ functions for the developer's use. Linker. Highly efficient linker to produce executables from object code. Debugger. Seamlessly integrated real-time, non-intrusive multi-mode debugger that enables debugging of highly optimized DSP algorithms. The developer can choose to debug in source code, assembly code, or mixed mode. Simulator. Device simulation models, enables design and simulation before the hardware arrival. Profiler. An analysis tool using a patented Binary Code Instrumentation (BCI) technique that enables the developer to identify program design inefficiencies. Version control. CodeWarrior(R) includes plug-ins for ClearCase, Visual SourceSafe, and CVS. -- Boot options: External memory. External host. UART. TDM. * Power: -- Requires separate power supplies for on-chip logic (1.6 V) and I/O (3.3 V) -- Provides low-power standby modes -- Includes optimized power management circuitry (instruction-dependent, peripheral-dependent, and mode-dependent). * Packaging: -- 0.8 mm pitch High Temperature Coefficient for Expansion Flip Chip Ceramic Ball-Grid Array (FC-CBGA (HCTE)) or Flip Chip Plastic Ball-Grid Array (FC-PBGA) (pre-production only) -- 431-pin -- 20 mm x 20 mm
Product Documentation
The documents listed in Table 1 are required for a complete description of the MSC8102 and are necessary to design properly with the part. Obtain documentation from a local Motorola distributor, semiconductor sales office, or a Motorola Literature Distribution Center. For documentation updates, visit the Motorola DSP website shown on the last page of this document. Table 1. MSC8102 Documentation
Name
MSC8102 Technical Data MSC8102 User's Guide MSC8102 Reference Manual
Description
MSC8102 features list and physical, electrical, timing, and package specifications User information include system functionality, getting started tutorial, and programming topics Detailed functional description of the MSC8102 memory and peripheral configuration, operation, and register programming
Order Number
MSC8102/D MSC8102UG/D MSC8102RM/D MNSC140CORE/D See the MSC8102 product website
SC140 DSP Core Reference Detailed description of the SC140 family processor core and instruction set Manual Application Notes Documents describing specific applications or optimized device operation including code examples
viii
Chapter 1
Signal/ Connection Description
The MSC8102 external signals are organized into functional groups, as shown in Table 1-1 and Figure 1-1.. Table 1-1 lists the functional groups, the number of signal connections in each group, and references the table that gives a detailed listing of multiplexed signals within each group. Figure 1-1. shows MSC8102 external signals organized by function. Table 1-1. MSC8102 Functional Signal Groupings
Functional Group
Power (VDD, VCC , and GND) Clock Reset and Configuration DSI, System Bus, and Interrupts Memory Controller General-Purpose Input/Output (GPIO), Time-Division Multiplexed (TDM) Interface, Universal Asynchronous Receiver/ Transmitter (UART), and Timers EOnce and JTAG Test Access Port Reserved (denotes connections that are always reserved)
Number of Signal Connections
158 3 4 210 16 32
Detailed Description
Table 1-2 on page 1-3 Table 1-3 on page 1-3 Table 1-4 on page 1-4 Table 1-5 on page 1-4 Table 1-6 on page 1-12 Table 1-7 on page 1-14
7 1
Table 1-8 on page 1-22 Table 1-9 on page 1-22
1-1
HD0/SWTE HD1/DSISYNC HD2/DSI64 HD3/MODCK1 HD4/MODCK2 HD5/CNFGS HD[6-31] HD[32-63]/D[32-63] HCID[0-3] HA[11-29] HWBS[0-3]/HDBS[0-3]/HWBE[0-3]/HDBE[0-3] HWBS[4-7]/HDBS[4-7]/HWBE[4-7]/HDBE[4-7]/ PWE[4-7]/PSDDQM[4-7]/PBS[4-7] HRDS/HRW/HRDE HBRST HDST0 HDST1 HCS HBCS HTA HCLKIN GPIO0/CHIP_ID0/IRQ4 GPIO1/TIMER0/CHIP_ID1/IRQ5 GPIO2/TIMER1/CHIP_ID2/IRQ6 GPIO3/TDM3TSYN/IRQ1 GPIO4/TDM3TCLK/IRQ2 GPIO5/TDM3TDAT/IRQ3 GPIO6/TDM3RSYN/IRQ4 GPIO7/TDM3RCLK/IRQ5 GPIO8/TDM3RDAT/IRQ6 GPIO9/TDM2TSYN/IRQ7 GPIO10/TDM2TCLK/IRQ8 GPIO11/TDM2TDAT/IRQ9 GPIO12/TDM2RSYN/IRQ10 GPIO13/TDM2RCLK/IRQ11 GPIO14/TDM2RDAT/IRQ12 GPIO15/TDM1TSYN/DREQ1 GPIO16/TDM1TCLK/DONE1/DRACK1 GPIO17/TDM1TDAT/DACK1 GPIO18/TDM1RSYN/DREQ2 GPIO19/TDM1RCLK/DACK2 GPIO20/TDM1RDAT GPIO21/TDM0TSYN GPIO22/TDM0TCLK/DONE2/DRACK2 GPIO23/TDM0TDAT/IRQ13 GPIO24/TDM0RSYN/IRQ14 GPIO25/TDM0RCLK/IRQ15 GPIO26/TDM0RDAT GPIO27/URXD/DREQ1 GPIO28/UTXD/DREQ2 GPIO29/CHIP_ID3 GPIO30/TIMER2/TMCLK GPIO31/TIMER3 TMS TDI TCK TRST TDO
1 1 DSI 1 1 BUS 1 1 & SYS 26 32 BUS 4 19 4 4 M E 1 M 1 C 1 1 D 1 1 S 1 I 1 1 GPIO 1 GPIO/ 1 TIMER 1 1 1 1 1 1 1 G 1 P 1 I 1 O 1 1 / 1 1 T 1 D 1 M 1 1 1 1 1 1 1 1 1 GPIO/ 1 UART 1 GPIO 1 GPIO/ 1 TIMER J 1 1 T 1 A 1 G 1
32 1 1 3 5 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 32 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 1 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

A[0-31] TT0 TT1 TT[2-4]/CS[5-7] CS[0-4] TSZ[0-3] TBST IRQ1/GBL IRQ3/BADDR31 IRQ2/BADDR30 IRQ5/BADDR29 BADDR28 BADDR27 BR BG DBG ABB/IRQ4 DBB/IRQ5 TS AACK ARTRY D[0-31] NC/DP0/DREQ1/EXT_BR2 IRQ1/DP1/DACK1/EXT_BG2 IRQ2/DP2/DACK2/EXT_DBG2 IRQ3/DP3/DREQ2/EXT_BR3 IRQ4/DP4/DACK3/EXT_DBG3 IRQ5/DP5/DACK4/EXT_BG3 IRQ6/DP6/DREQ3 IRQ7/DP7/DREQ4 TA TEA NMI NMI_OUT PSDVAL IRQ7/INT_OUT BCTL0 BCTL1/CS[5] BM[0-2]/TC[0-2]/BNKSEL[0-2] ALE PWE[0-3]/PSDDQM[0-3]/PBS[0-3] PSDA10/PGPL0 PSDWE/PGPL1 POE/PSDRAS/PGPL2 PSDCAS/PGPL3 PGTA/PUPMWAIT/PGPL4/PPBS PSDAMUX/PGPL5 TEST EE0 EE1 CLKOUT DLLIN CLKIN PORESET HRESET SRESET RSTCONF
S Y S T E M B U S
M E M C S Y S
T S T C L K R E S E T
Power signals include: VDD , VDDH, VCCSYN, GND, and GNDSYN.
Figure 1-1. MSC8102 External Signals
1-2
Power Signals
1.1 Power Signals
Table 1-2. Power and Ground Signal Inputs
Signal Name
V DD
Description
Internal Logic Power V DD dedicated for use with the device core. The voltage should be well-regulated and the input should be provided with an extremely low impedance path to the VDD power rail. Input/Output Power This source supplies power for the I/O buffers. The user must provide adequate external decoupling capacitors. System PLL Power V CC dedicated for use with the system Phase Lock Loop (PLL). The voltage should be well-regulated and the input should be provided with an extremely low impedance path to the VCC power rail. System Ground An isolated ground for the internal processing logic and I/O buffers. This connection must be tied externally to all chip ground connections, except GNDSYN. The user must provide adequate external decoupling capacitors. System PLL Ground Ground dedicated for system PLL use. The connection should be provided with an extremely low-impedance path to ground.
VDDH
V CCSYN
GND
GND SYN
1.2 Clock Signals
Table 1-3. Clock Signals
Signal Name
CLKIN CLKOUT DLLIN
Type
Input Output Input
Signal Description
Clock In Primary clock input to the MSC8102 PLL. Clock Out The bus clock. DLLIN Synchronizes with an external device.
1-3
Reset and Configuration Signals
1.3 Reset and Configuration Signals
Table 1-4. Reset and Configuration Signals
Signal Name
PORESET RSTCONF
Type
Input Input
Signal Description
Power-On Reset When asserted, this line causes the MSC8102 to enter power-on reset state. Reset Configuration1 Used during reset configuration sequence of the chip. A detailed explanation of its function is provided in the MSC8102 Reference Manual. This signal is sampled upon deassertion of PORESET. Hard Reset When asserted, this open-drain line causes the MSC8102 to enter hard reset state. Soft Reset When asserted, this open-drain line causes the MSC8102 to enter soft reset state.
HRESET SRESET Note:
Input Input
When PORESET is deasserted, the MSC8102 also samples the following signals: * BM[0-2]--Selects the boot mode. * MODCK[1-2]--Selects the clock configuration. * SWTE--Enables the software watchdog timer. * DSISYNC, DSI64, CNFGS, and CHIP_ID[0-3]--Configures the DSI. Refer to Table 1-5 for details on these signals.
1.4 Direct Slave Interface, System Bus, and Interrupt Signals
The direct slave interface (DSI) is combined with the system bus because they share some common signal lines. Individual assignment of a signal to a specific signal line is configured through internal registers. Table 1-5 describes the signals in this group. Note: Although there are fifteen interrupt request (IRQ) connections to the core processors, there are multiple external lines that can connect to these internal signal lines. After reset, the default configuration enables only IRQ[1-7], but includes two input lines each for IRQ[1-3] and IRQ7. The designer must select one line for each required interrupt and reconfigure the other external signal line or lines for alternate functions. Additional alternate IRQ lines and IRQ[8-15] are enabled through the GPIO signal lines. Table 1-5. DSI, System Bus, and Interrupt Signals
Signal Name
HD0
Type
Input/ Output Input Input/ Output Input Host Data Bus 0 Bit 0 of the DSI data bus.
Description
SWTE HD1
Software Watchdog Timer Disable. It is sampled on the rising edge of PORESET signal. Host Data Bus 1 Bit 1 of the DSI data bus. DSI Synchronous Distinguishes between synchronous and asynchronous operation of the DSI. It is sampled on the rising edge of PORESET signal.
DSISYNC
1-4
Direct Slave Interface, System Bus, and Interrupt Signals
Table 1-5. DSI, System Bus, and Interrupt Signals (Continued)
Signal Name
HD2
Type
Input/ Output Input Host Data Bus 2 Bit 2 of the DSI data bus.
Description
DSI64
DSI 64 Defines the width of the DSI and SYSTEM Data buses. It is sampled on the rising edge of PORESET signal. Host Data Bus 3 Bit 3 of the DSI data bus. Clock Mode 1 Defines the clock frequencies. It is sampled on the rising edge of PORESET signal. Host Data Bus 4 Bit 4 of the DSI data bus. Clock Mode 2 Defines the clock frequencies. It is sampled on the rising edge of PORESET signal. Host Data Bus 5 Bit 5 of the DSI data bus. Configuration Source One signal out of two that indicates reset configuration mode. It is sampled on the rising edge of PORESET signal.
HD3
Input/ Output Input Input/ Output Input Input/ Output Input
MODCK1 HD4
MODCK2 HD5
CNFGS
HD[6-31] HD[32-63]
Input/O Host Data Bus 6-31 utput Bits 6-31 of the DSI data bus. Input/O Host Data Bus 32-63 utput Bits 32-63 of the DSI data bus. Input/O System Bus Data 32-63 utput In write transactions, the bus master drives the valid data on this bus. In read transactions, the slave drives the valid data on this bus. Input Host Chip ID 0-3 Carries the chip ID of the DSI. The DSI is accessed only if HCS is asserted and HCID[0-3] matches the Chip_ID, or if HBCS is asserted. Host Bus Address 11-29 Used by external host to access the internal address space. Host Write Byte Strobes (In Asynchronous dual mode) One bit per byte is used as a strobe for host write accesses. Host Data Byte Strobe (in Asynchronous single mode) One bit per byte is used as a strobe for host read or write accesses Host Write Byte Enable (In Synchronous dual mode) One bit per byte is used to indicate a valid data byte for host read or write accesses. Host Data Byte Enable (in Synchronous single mode) One bit per byte is used as a strobe enable for host write accesses
D[32-63]
HCID[0-3]
HA[11-29] HWBS[0-3]
Input Input
HDBS[0-3]
Input
HWBE[0-3]
Input
HDBE[0-3]
Input
1-5
Direct Slave Interface, System Bus, and Interrupt Signals
Table 1-5. DSI, System Bus, and Interrupt Signals (Continued)
Signal Name
HWBS[4-7]
Type
Input
Description
Host Write Byte Strobes (In Asynchronous dual mode) One bit per byte is used as a strobe for host write accesses. Host Data Byte Strobe (in Asynchronous single mode) One bit per byte is used as a strobe for host read or write accesses Host Write Byte Enable (In Synchronous dual mode) One bit per byte is used to indicate a valid data byte for host write accesses. Host Data Byte Enable (in Synchronous single mode) One bit per byte is used as a strobe enable for host read or write accesses System Bus Write Enable Outputs of the bus general-purpose chip-select machine (GPCM). These pins select byte lanes for write operations. System Bus SDRAM DQM From the SDRAM control machine. These pins select specific byte lanes of SDRAM devices. System Bus UPM Byte Select From the UPM in the memory controller, these signals select specific byte lanes during memory operations. The timing of these pins is programmed in the UPM. The actual driven value depends on the address and size of the transaction and the port size of the accessed device. Host Read Data Strobe (In Asynchronous dual mode) Used as a strobe for host read accesses. Host Read/Write Select (in Asynchronous/Synchronous single mode) Host read/write select. Host Read Data Enable (In Synchronous dual mode) Indicates valid data for host read accesses. Host Burst The host asserts this pin to indicate that the current transaction is a burst transaction in synchronous mode only. Host Data structure 0 Defines the data structure of the host access in DSI little-endian mode. Host Data structure 1 Defines the data structure of the host access in DSI little-endian mode. Host Chip Select DSI chip select. The DSI is accessed only if HCS is asserted and HCID[0-3] matches the Chip_ID. Host Broadcast Chip Select DSI chip select for broadcast mode. Enables more than one DSI to share the same host chip-select pin for broadcast write accesses. Host Transfer Acknowledge Upon a read access, indicates to the host when the data on the data bus is valid. Upon a write access, indicates to the host that the data on the data bus was written to the DSI write buffer. Host Clock Input Host clock signal for DSI synchronous mode.
HDBS[4-7]
Input
HWBE[4-7]
Input
HDBE[4-7]
Input
PWE[4-7]
Output
PSDDQM[4-7]
Output
PBS[4-7]
Output
HRDS
Input
HRW
Input
HRDE HBRST
Input Input
HDST0 HDST1 HCS
Input Input Input
HBCS
Input
HTA
Output
HCLKIN
Input
1-6
Direct Slave Interface, System Bus, and Interrupt Signals
Table 1-5. DSI, System Bus, and Interrupt Signals (Continued)
Signal Name
A[0-31]
Type
Input/ Output
Description
Address Bus When the MSC8102 is in external master bus mode, these pins function as the system address bus. The MSC8102 drives the address of its internal bus masters and responds to addresses generated by external bus masters. When the MSC8102 is in internal master bus mode, these pins are used as address lines connected to memory devices and are controlled by the MSC8102 memory controller. Bus Transfer Type 0 The bus master drives this pins during the address tenure to specify the type of the transaction. Bus Transfer Type 1 The bus master drives this pins during the address tenure to specify the type of the transaction. Some applications use only the TT1 signal, for example, from MSC8102 to MSC8102 or MSC8102 to MSC8101 and vice versa. In these applications, TT1 functions as read/write signal. Bus Transfer Type 2-4 The bus master drives these pins during the address tenure to specify the type of the transaction. Chip Select 5-7 Enables specific memory devices or peripherals connected to the system bus. Chip Select 0-4 Enables specific memory devices or peripherals connected to the system bus. Transfer Size 0-3 The bus master drives these pins with a value indicating the number of bytes transferred in the current transaction. Bus Transfer Burst The bus master asserts this pin to indicate that the current transaction is a burst transaction (transfers eight words). Interrupt Request 11 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. Global1 When a master within the MSC8102 initiates a bus transaction, it drives this pin. Assertion of this pin indicates that the transfer is global and should be snooped by caches in the system. Interrupt Request 31 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. Burst Address 311 There are five burst address output pins, which are outputs of the memory controller. These pins connect directly to burstable memory devices without internal address incrementors controlled by the MSC8102 memory controller. Interrupt Request 21 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. Burst Address 301 There are five burst address output pins, which are outputs of the memory controller. These pins connect directly to burstable memory devices without internal address incrementors controlled by the MSC8102 memory controller.
TT0
Input/ Output Input/ Output
TT1
TT[2-4]
Input/ Output
CS[5-7] CS[0-4] TSZ[0-3]
Output Output Input/ Output Input/ Output Input
TBST
IRQ1
GBL
Output
IRQ3
Input
BADDR31
Output
IRQ2
Input
BADDR30
Output
1-7
Direct Slave Interface, System Bus, and Interrupt Signals
Table 1-5. DSI, System Bus, and Interrupt Signals (Continued)
Signal Name
IRQ5
Type
Input
Description
Interrupt Request 51 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. Bus Burst Address 291 There are five burst address output pins, which are outputs of the memory controller. These pins connect directly to burstable memory devices without internal address incrementors controlled by the MSC8102 memory controller. Burst Address 28 There are five burst address output pins, which are outputs of the memory controller. These pins connect directly to burstable memory devices without internal address incrementors controlled by the MSC8102 memory controller. Burst Address 27 There are five burst address output pins, which are outputs of the memory controller. These pins connect directly to burstable memory devices without internal address incrementors controlled by the MSC8102 memory controller. Bus Request2 When an external arbiter is used, the MSC8102 asserts this pin as an output to request ownership of the bus. When the MSC8102 controller is used as an internal arbiter, an external master asserts this pin as an input to request bus ownership. Bus Grant 2 When the MSC8102 acts as an internal arbiter, it asserts this pin as an output to grant bus ownership to an external bus master. When an external arbiter is used, it asserts this pin as an input to grant bus ownership to the MSC8102. Data Bus Grant2 When the MSC8102 acts as an internal arbiter, it asserts this pin as an output to grant data bus ownership to an external bus master. When an external arbiter is used, it asserts this pin as an input to grant data bus ownership to the MSC8102. Address Bus Busy1 The MSC8102 asserts this pin as an output for the duration of the address bus tenure. Following an AACK, which terminates the address bus tenure, the MSC8102 deasserts ABB for a fraction of a bus cycle and then stops driving this pin. The MSC8102 does not assume bus ownership as long as it senses this pin is asserted as an input by an external bus master. Interrupt Request 4 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. Data Bus Busy1 The MSC8102 asserts this pin as an output for the duration of the data bus tenure. Following a TA, which terminates the data bus tenure, the MSC8102 deasserts DBB for a fraction of a bus cycle and then stops driving this pin. The MSC8102 does not assume data bus ownership as long as it senses that this pin is asserted as an input by an external bus master. Interrupt Request 5 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. Bus Transfer Start Assertion of this pin signals the beginning of a new address bus tenure. The MSC8102 asserts this signal when one of its internal bus masters begins an address tenure. When the MSC8102 senses that this pin is asserted by an external bus master, it responds to the address bus tenure as required (snoop if enabled, access internal MSC8102 resources, memory controller support). Address Acknowledge A bus slave asserts this signal to indicate that it has identified the address tenure. Assertion of this signal terminates the address tenure.
BADDR29
Output
BADDR28
Output
BADDR27
Output
BR
Input/ Output
BG
Input/ Output
DBG
Input/ Output
ABB
Input/ Output
IRQ4
Input
DBB
Input/ Output
IRQ5
Input
TS
Input/ Output
AACK
Input/ Output
1-8
Direct Slave Interface, System Bus, and Interrupt Signals
Table 1-5. DSI, System Bus, and Interrupt Signals (Continued)
Signal Name
ARTRY
Type
Input/ Output
Description
Address Retry Assertion of this signal indicates that the bus master should retry the bus transaction. An external master asserts this signal to enforce data coherency with its caches and to prevent deadlock situations. Data Bus Bits 0-31 In write transactions, the bus master drives the valid data on this bus. In read transactions, the slave drives the valid data on this bus. The primary configuration selection (default after reset) is reserved. System Bus Data Parity 0 The agent that drives the data bus also drives the data parity signals. The value driven on the data parity 0 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 0 and D[0-7]. DMA Request 1 Used by an external peripheral to request DMA service. External Bus Request 2 An external master asserts this pin to request bus ownership from the internal arbiter. Interrupt Request 1 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. System Bus Data Parity 1 The agent that drives the data bus also drives the data parity signals. The value driven on the data parity 1 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 1 and D[8-15]. DMA Acknowledge 1 The DMA drives this output to acknowledge the DMA transaction on the bus. External Bus Grant 22 The MSC8102 asserts this pin to grant bus ownership to an external bus master. Interrupt Request 2 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. System Bus Data Parity 2 The agent that drives the data bus also drives the data parity signals. The value driven on the data parity 2 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 2 and D[16-23]. DMA Acknowledge 2 The DMA drives this output to acknowledge the DMA transaction on the bus. External Data Bus Grant 22 The MSC8102 asserts this pin to grant data bus ownership to an external bus master.
D[0-31]
Input/ Output Input Input/ Output
Reserved DP0
DREQ1
Input
EXT_BR2 IRQ1
Input Input
DP1
Input/ Output
DACK1
Output
EXT_BG2 IRQ2
Output Input
DP2
Input/ Output
DACK2
Output
EXT_DBG2
Output
1-9
Direct Slave Interface, System Bus, and Interrupt Signals
Table 1-5. DSI, System Bus, and Interrupt Signals (Continued)
Signal Name
IRQ3
Type
Input
Description
Interrupt Request 3 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. System Bus Data Parity 3 The agent that drives the data bus also drives the data parity signals. The value driven on the data parity 3 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 3 and D[24-31]. DMA Request 2 Used by an external peripheral to request DMA service. External Bus Request 32 An external master should assert this pin to request bus ownership from the internal arbiter. Interrupt Request 4 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. System Bus Data Parity 4 The agent that drives the data bus also drives the data parity signals. The value driven on the data parity 4 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 4 and D[32-39]. DMA Acknowledge 3 The DMA drives this output to acknowledge the DMA transaction on the bus. External Data Bus Grant 32 The MSC8102 asserts this pin to grant data bus ownership to an external bus master. Interrupt Request 5 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. System Bus Data Parity 5 The agent that drives the data bus also drives the data parity signals. The value driven on the data parity 5 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 5 and D[40-47]. DMA Acknowledge 4 The DMA drives this output to acknowledge the DMA transaction on the bus. External Bus Grant 32 The MSC8102 asserts this pin to grant bus ownership to an external bus. Interrupt Request 6 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. System Bus Data Parity 6 The agent that drives the data bus also drives the data parity signals. The value driven on the data parity 6 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 6 and D[48-55]. DMA Request 3 Used by an external peripheral to request DMA service.
DP3
Input/ Output
DREQ2
Input
EXT_BR3
Input
IRQ4
Input
DP4
Input/ Output
DACK3
Output
EXT_DBG3 IRQ5
Output Input
DP5
Input/ Output
DACK4
Output
EXT_BG3 IRQ6
Output Input
DP6
Input/ Output
DREQ3
Input
1-10
Direct Slave Interface, System Bus, and Interrupt Signals
Table 1-5. DSI, System Bus, and Interrupt Signals (Continued)
Signal Name
IRQ7
Type
Input
Description
Interrupt Request 7 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. System Bus Data Parity 7 The agent that drives the data bus also drives the data parity signals. The value driven on the data parity 7 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 7 and D[56-63]. DMA Request 4 Used by an external peripheral to request DMA service. Transfer Acknowledge Indicates that a data beat is valid on the data bus. For single-beat transfers, TA assertion indicates the termination of the transfer. For burst transfers, TA is asserted eight times to indicate the transfer of eight data beats, with the last assertion indicating the termination of the burst transfer. Transfer Error Acknowledge Assertion indicates a failure of the data tenure transaction.The masters within the MSC8102 monitor the state of this pin. The MSC8102 internal bus monitor can assert this pin if it identifies a bus transfer that does not complete. Non-Maskable Interrupt When an external device asserts this line, it generates an non-maskable interrupt in the MSC8102, which is processed internally (default) or is directed to an external host for processing (see NMI_OUT). Non-Maskable Interrupt Output An open-drain pin driven from the MSC8102 internal interrupt controller. Assertion of this output indicates that a non-maskable interrupt is pending in the MSC8102 internal interrupt controller, waiting to be handled by an external host. Port Size Data Valid Indicates that a data beat is valid on the data bus. The difference between the TA pin and the PSDVAL pin is that the TA pin is asserted to indicate data transfer terminations, while the PSDVAL signal is asserted with each data beat movement. When TA is asserted, PSDVAL is always asserted. However, when PSDVAL is asserted, TA is not necessarily asserted. For example, if the DMA initiates a double word (2 x 64 bits) transaction to a memory device with a 32-bit port size, PSDVAL is asserted three times without TA and, finally, both pins are asserted to terminate the transfer. Interrupt Request 7 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. Interrupt Output Assertion of this output indicates that an unmasked interrupt is pending in the MSC8102 internal interrupt controller.
DP7
Input/ Output
DREQ4 TA
Input Input/ Output
TEA
Input/ Output
NMI
Input
NMI_OUT
Output
PSDVAL
Input/ Output
IRQ7
Input
INT_OUT
Output
Notes:
1. 2.
See the System Interface Unit (SIU) chapter in the MSC8102 Reference Manual for details on how to configure these pins. When used as the bus control arbiter, the MSC8102 can support up to three external bus masters. Each master uses its own set of Bus Request, Bus Grant, and Data Bus Grant signals (BR/BG/DBG, EXT_BR2/EXT_BG2/EXT_DBG2, and EXT_BR3/EXT_BG3/EXT_DBG3). Each of these signal sets must be configured to indicate whether the external master is or is not a MSC8102 master device. See the Bus Configuration Register (BCR) description in the System Interface Unit (SIU) chapter in the MSC8102 Reference Manual for details on how to configure these pins. The second and third set of pins is defined by EXT_xxx to indicate that they can only be used with external master devices. The first set of pins (BR/BG/DBG) have a dual function. When the MSC8102 is not the bus arbiter, these signals (BR/BG/DBG) are used by the MSC8102 to obtain master control of the bus.
1-11
Memory Controller Signals
1.5 Memory Controller Signals
Refer to the Memory Controller chapter in the MSC8102 Reference Manual for detailed information about configuring these signals. Table 1-6. Memory Controller Signals
Signal Name
BCTL0
Type
Output
Description
System Bus Buffer Control 0 Controls buffers on the data bus. Usually used with BCTL1. The exact function of this pin is defined by the value of SIUMCR[BCTLC]. System Bus Buffer Control 1 Controls buffers on the data bus. Usually used with BCTL0. The exact function of this pin is defined by the value of SIUMCR[BCTLC]. System and Local Bus Chip Select 5 Enables specific memory devices or peripherals connected to MSC8102 buses. Boot Mode 0-2 Defines the boot mode of the MSC8102. This signal is sampled on PORESET deassertion. Transfer Code 0-2 The bus master drives these pins during the address tenure to specify the type of the code. Bank Select 0-2 Selects the SDRAM bank when the MSC8102 is in 60x-compatible bus mode. Address Latch Enable Controls the external address latch used in an external master bus. System Bus Write Enable Outputs of the bus general-purpose chip-select machine (GPCM). These pins select byte lanes for write operations. System Bus SDRAM DQM From the SDRAM control machine. These pins select specific byte lanes of SDRAM devices. System Bus UPM Byte Select From the UPM in the memory controller, these signals select specific byte lanes during memory operations. The timing of these pins is programmed in the UPM. The actual driven value depends on the address and size of the transaction and the port size of the accessed device. System Bus SDRAM A10 From the bus SDRAM controller. The precharge command defines which bank is precharged. When the row address is driven, it is a part of the row address. When column address is driven, it is a part of column address. System Bus UPM General-Purpose Line 0 One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed in the UPM. System Bus SDRAM Write Enable From the bus SDRAM controller. Should connect to SDRAM WE input. System Bus UPM General-Purpose Line 1 One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed in the UPM.
BCTL1
Output
CS5 BM[0-2]
Output Input
TC[0-2]
Input/ Output
BNKSEL[0-2] ALE PWE[0-3]
Output Output Output
PSDDQM[0-3]
Output
PBS[0-3]
Output
PSDA10
Output
PGPL0
Output
PSDWE
Output
PGPL1
Output
1-12
Memory Controller Signals
Table 1-6. Memory Controller Signals (Continued)
Signal Name
POE
Type
Output
Description
System Bus Output Enable From the bus GPCM. Controls the output buffer of memory devices during read operations. System Bus SDRAM RAS From the bus SDRAM controller. Should connect to SDRAM RAS input. System Bus UPM General-Purpose Line 2 One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed in the UPM. System Bus SDRAM CAS From the bus SDRAM controller. Should connect to SDRAM CAS input. System Bus UPM General-Purpose Line 3 One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed in the UPM. System GPCM TA Terminates external transactions during GPCM operation. Requires an external pull-up resistor for proper operation. System Bus UPM Wait An external device holds this pin low to force the UPM to wait until the device is ready to continue the operation. System Bus UPM General-Purpose Line 4 One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed in the UPM. System Bus Parity Byte Select In systems that store data parity in a separate chip, this output is used as the byte-select for that chip. System Bus SDRAM Address Multiplexer Controls the system bus SDRAM address multiplexer when the MSC8102 is in external master mode. System Bus UPM General-Purpose Line 5 One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed in the UPM.
PSDRAS
Output
PGPL2
Output
PSDCAS
Output
PGPL3
Output
PGTA
Input
PUPMWAIT
Input
PGPL4
Output
PPBS
Output
PSDAMUX
Output
PGPL5
Output
1-13
GPIO, TDM, UART, and Timer Signals
1.6 GPIO, TDM, UART, and Timer Signals
The general-purpose input/output (GPIO), time-division multiplexed (TDM), universal asynchronous receiver/transmitter (UART), and timer signals are grouped together because they use a common set of signal lines. Individual assignment of a signal to a specific signal line is configured through internal registers. Table 1-7 describes the signals in this group. Table 1-7. GPIO, TDM, UART, and Timer Signals
Signal Name
GPIO0
Type
Input/ Output
Description
General-Purpose Input Output 0 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. Chip ID 0 Determines the chip ID of the MSC8102 DSI. It is sampled on the rising edge of PORESET signal. General-Purpose Input Output 1 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. Timer 0 Each signal is configured as either input to or output from the counter. See the MSC8102 Reference for configuration details. Chip ID 1 Determines the chip ID of the MSC8102 DSI. It is sampled on the rising edge of PORESET signal. General-Purpose Input Output 2 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8102 Reference Manual. Timer 1 Each signal is configured as either input to or output from the counter. For the configuration of the pin direction, refer to the MSC8102 Reference Manual. Chip ID 2 Determines the chip ID of the MSC8102 DSI. It is sampled on the rising edge of PORESET signal. General-Purpose Input Output 3 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8102 Reference Manual GPIO programing model. TDM3 Transmit Frame Sync Transmit frame sync for TDM 3. Interrupt Request 1 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core.
CHIP_ID0
Input
GPIO1
Input/ Output
TIMER0
Input/ Output
CHIP_ID1
Input
GPIO2
Input/ Output
TIMER1
Input/ Output
CHIP_ID2
Input
GPIO3
Input/ Output
TDM3TSYN
Input/ Output Input
IRQ1
1-14
GPIO, TDM, UART, and Timer Signals
Table 1-7. GPIO, TDM, UART, and Timer Signals (Continued)
Signal Name
GPIO4
Type
Input/ Output
Description
General-Purpose Input Output 4 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8102 Reference Manual GPIO programing model. TDM3 Transmit Clock Transmit Clock for TDM 3 Interrupt Request 2 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. General-Purpose Input/Output 5 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8102 Reference Manual GPIO programing model. TDM3 Serial Transmitter Data The serial transmit data signal for TDM 3. As an output, it provides the DATA_D signal for TDM 3. For configuration details, refer to the MSC8102 Reference Manual chapter describing TDM operation. Interrupt Request 3 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. General-Purpose Input Output 6 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8102 Reference Manual GPIO programing model. TDM3 Receive Frame Sync The receive sync signal for TDM 3. As an input, this can be the DATA_B data signal for TDM 3.For configuration details, refer to the MSC8102 Reference Manual chapter describing TDM operation. Interrupt Request 4 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. General-Purpose Input Output 7 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8102 Reference Manual GPIO programing model. TDM3 Receive Clock The receive clock signal for TDM 3. As an output, this can be the DATA_C data signal for TDM 3. For configuration details, refer to the MSC8102 Reference Manual chapter describing TDM operation. Interrupt Request 5 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core.
TDM3TCLK
Input
IRQ2
Input
GPIO5
Input/ Output
TDM3TDAT
Input/ Output
IRQ3
Input
GPIO6
Input/ Output
TDM3RSYN
Input/ Output
IRQ4
Input
GPIO7
Input/ Output
TDM3RCLK
Input/ Output
IRQ5
Input
1-15
GPIO, TDM, UART, and Timer Signals
Table 1-7. GPIO, TDM, UART, and Timer Signals (Continued)
Signal Name
GPIO8
Type
Input/ Output
Description
General-Purpose Input Output 8 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8102 Reference Manual GPIO programing model. TDM3 Serial Receiver Data The receive data signal for TDM 3. As an input, this can be the DATA_A data signal for TDM 3. For configuration details, refer to the MSC8102 Reference Manual chapter describing TDM operation. Interrupt Request 6 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. General-Purpose Input Output 9 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8102 Reference Manual GPIO programing model. TDM2 Transmit frame Sync Transmit Frame Sync for TDM 2. Interrupt Request 7 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. General-Purpose Input Output 10 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8102 Reference Manual GPIO programing model. TDM 2 Transmit Clock Transmit Clock for TDM 2. Interrupt Request 8 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. General-Purpose Input Output 11 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8102 Reference Manual GPIO programing model. TDM2 Serial Transmitter Data The transmit data signal for TDM 2. As an output, this can be the DATA_D data signal for TDM 2. For configuration details, refer to the MSC8102 Reference Manual chapter describing TDM operation. Interrupt Request 9 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core.
TDM3RDAT
Input/ Output
IRQ6
Input
GPIO9
Input/ Output
TDM2TSYN
Input/ Output Input
IRQ7
GPIO10
Input/ Output
TDM2TCLK
Input
IRQ8
Input
GPIO11
Input/ Output
TDM2TDAT
Input/ Output
IRQ9
Input
1-16
GPIO, TDM, UART, and Timer Signals
Table 1-7. GPIO, TDM, UART, and Timer Signals (Continued)
Signal Name
GPIO12
Type
Input/ Output
Description
General-Purpose Input Output 12 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8102 Reference Manual GPIO programing model. TDM2 Receive Frame Sync The receive sync signal for TDM 2. As an input, this can be the DATA_B data signal for TDM 2. For configuration details, refer to the MSC8102 Reference Manual chapter describing TDM operation. Interrupt Request 10 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. General-Purpose Input Output 13 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8102 Reference Manual GPIO programing model. TDM2 Receive Clock The receive clock signal for TDM 2. As an input, this can be the DATA_C data signal for TDM 2. For configuration details, refer to the MSC8102 Reference Manual chapter describing TDM operation. Interrupt Request 11 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. General-Purpose Input Output 14 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8102 Reference Manual GPIO programing model. TDM2 Serial Receiver Data The receive data signal for TDM 2. As an input, this can be the DATA_A data signal for TDM 2. For configuration details, refer to the MSC8102 Reference Manual chapter describing TDM operation. Interrupt Request 12 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. General-Purpose Input Output 15 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8102 Reference Manual GPIO programing model. TDM1 Transmit frame Sync Transmit Frame Sync for TDM 1. DMA Request 1 Used by an external peripheral to request DMA service.
TDM2RSYN
Input/ Output
IRQ10
Input
GPIO13
Input/ Output
TDM2RCLK
Input/ Output
IRQ11
Input
GPIO14
Input/ Output
TDM2RDAT
Input/ Output Input
IRQ12
Input
GPIO15
Input/ Output
TDM1TSYN
Input/ Output Input
DREQ1
1-17
GPIO, TDM, UART, and Timer Signals
Table 1-7. GPIO, TDM, UART, and Timer Signals (Continued)
Signal Name
GPIO16
Type
Input/ Output
Description
General-Purpose Input Output 16 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8102 Reference Manual GPIO programing model. TDM1 Transmit Clock Transmit Clock for TDM 1. DMA Done 1 Signifies that the channel must be terminated. If the DMA generates DONE, the channel handling this peripheral is inactive. As an input to the DMA, DONE closes the channel much like a normal channel closing. See the MSC8102 Reference Manual chapters on DMA and GPIO for information on configuring the DRACK or DONE mode and pin direction.
TDM1TCLK
Input
DONE1
Input/ Output
DRACK1
Output
DMA Data Request Acknowledge 1 Asserted by the DMA controller to indicate that the DMA controller has sampled the peripheral request. General-Purpose Input Output 17 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8102 Reference Manual GPIO programing model. TDM1 Serial Transmitter Data The transmit data signal for TDM 1. As an output, this can be the DATA_D data signal for TDM 1.For configuration details, refer to the MSC8102 Reference Manual chapter describing TDM operation. DMA Acknowledge 1 The DMA controller drives this output to acknowledge the DMA transaction on the bus. General-Purpose Input Output 18 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8102 Reference Manual GPIO programing model. TDM1 Receive Frame Sync The receive sync signal for TDM 1. As an input, this can be the DATA_B data signal for TDM 1. For configuration details, refer to the MSC8102 Reference Manual chapter describing TDM operation. DMA Request 1 Used by an external peripheral to request DMA service. General-Purpose Input Output 19 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8102 Reference Manual GPIO programing model. TDM1 Receive Clock The receive clock signal for TDM 1. As an input, this can be the DATA_C data signal for TDM 1. For configuration details, refer to the MSC8102 Reference Manual chapter describing TDM operation. DMA Acknowledge 2 The DMA controller drives this output to acknowledge the DMA transaction on the bus.
GPIO17
Input/ Output
TDM1TDAT
Input/ Output
DACK1 GPIO18
Output Input/ Output
TDM1RSYN
Input/ Output
DREQ2 GPIO19
Input Input/ Output
TDM1RCLK
Input/ Output
DACK2
Output
1-18
GPIO, TDM, UART, and Timer Signals
Table 1-7. GPIO, TDM, UART, and Timer Signals (Continued)
Signal Name
GPIO20
Type
Input/ Output
Description
General-Purpose Input Output 20 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8102 Reference Manual GPIO programing model. TDM1 Serial Receiver Data The receive data signal for TDM 1. As an input, this can be the DATA_A data signal for TDM 1. For configuration details, refer to the MSC8102 Reference Manual chapter describing TDM operation. General-Purpose Input Output 21 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8102 Reference Manual GPIO programing model. TDM0 Transmit frame Sync Transmit Frame Sync for TDM 0. General-Purpose Input Output 22 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs.For details, refer to the MSC8102 Reference Manual GPIO programing model. TDM 0 Transmit Clock Transmit Clock for TDM 0. DMA Done 2 Signifies that the channel must be terminated. If the DMA generates DONE, the channel handling this peripheral is inactive. As an input to the DMA, DONE closes the channel much like a normal channel closing. Note: See the MSC8102 Reference Manual chapters on DMA and GPIO for information on configuring the DRACK or DONE mode and pin direction.
TDM1RDAT
Input/ Output
GPIO21
Input/ Output
TDM0TSYN GPIO22
Input/ Output Input/ Output
TDM0TCLK
Input
DONE2
Input/ Output
DRACK2
Output
DMA Data Request Acknowledge 2 Asserted by the DMA controller to indicate that the DMA controller has sampled the peripheral request. General-Purpose Input Output 23 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8102 Reference Manual GPIO programing model. TDM0 Serial Transmitter Data The transmit data signal for TDM 0. As an output, this can be the DATA_D data signal for TDM 0. For configuration details, refer to the MSC8102 Reference Manual chapter describing TDM operation. Interrupt Request 13 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core.
GPIO23
Input/ Output
TDM0TDAT
Input/ Output
IRQ13
Input
1-19
GPIO, TDM, UART, and Timer Signals
Table 1-7. GPIO, TDM, UART, and Timer Signals (Continued)
Signal Name
GPIO24
Type
Input/ Output
Description
General-Purpose Input Output 24 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8102 Reference Manual GPIO programing model. TDM0 Receive Frame Sync The receive sync signal for TDM 0. As an input, this can be the DATA_B data signal for TDM 0. For configuration details, refer to the MSC8102 Reference Manual chapter describing TDM operation. Interrupt Request 14 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. General-Purpose Input Output 25 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8102 Reference Manual GPIO programing model. TDM0 Receive Clock The receive clock signal for TDM 0. As an input, this can be the DATA_C data signal for TDM 0. For configuration details, refer to the MSC8102 Reference Manual chapter describing TDM operation. Interrupt Request 15 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. General-Purpose Input Output 26 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8102 Reference Manual GPIO programing model. TDM0 Serial Receiver Data The receive data signal for TDM 0. As an input, this can be the DATA_A data signal for TDM 0. For configuration details, refer to the MSC8102 Reference Manual chapter describing TDM operation. General-Purpose Input Output 27 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8102 Reference Manual GPIO programing model. UART Receive Data General-Purpose Input Output 28 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8102 Reference Manual GPIO programing model. UART Transmit Data General-Purpose Input Output 29 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8102 Reference Manual GPIO programing model. Chip ID 3 Determines the chip ID of the MSC8102 DSI. It is sampled on the rising edge of PORESET signal.
TDM0RSYN
Input/ Output
IRQ14
Input
GPIO25
Input/ Output
TDM0RCLK
Input/ Output
IRQ15
Input
GPIO26
Input/ Output
TDM0RDAT
Input/ Output
GPIO27
Input/ Output
URXD GPIO28
Input Input/ Output
UTXD GPIO29
Output Input/ Output
CHIP_ID3
Input
1-20
GPIO, TDM, UART, and Timer Signals
Table 1-7. GPIO, TDM, UART, and Timer Signals (Continued)
Signal Name
GPIO30
Type
Input/ Output
Description
General-Purpose Input Output 30 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs.For details, refer to the MSC8102 Reference Manual GPIO programing model. Timer 2 Each signal is configured as either input to the counter or output from the counter. For the configuration of the pin direction, refer to the MSC8102 Reference Manual. External TIMER Clock An external timer can connect directly to the SIU as the SIU Clock. General-Purpose Input Output 31 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8102 Reference Manual GPIO programing model. Timer 3 Each signal is configured as either input to or output from the counter. For the configuration of the pin direction, refer to the MSC8102 Reference Manual.
TIMER2
Input/ Output
TMCLK GPIO31
Input Input/ Output
TIMER3
Input/ Output
1-21
EOnCE Event and JTAG Test Access Port Signals
1.7 EOnCE Event and JTAG Test Access Port Signals
The MSC8102 uses two sets of debugging signals for the two types of internal debugging modules: EOnCE and the JTAG TAP controller. Each internal SC140 core has an EOnce module, but they are all accessed externally by the same two signals EE0 and EE1. The MSC8102 supports the standard set of Test Access Port (TAP) signals defined by IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture specification and described in Table 1-8.
Table 1-8. JTAG Test Access Port Signals
Signal Name
EE0 EE1 TCK TDI TDO
Type
Input Output Input Input Output
Signal Description
EOnCE Event Bit 0 Used for putting the internal SC140 cores into Debug mode. EOnCE Event Bit 1 Indicates that at least one on-chip SC140 core is in Debug mode. Test Clock--A test clock signal for synchronizing JTAG test logic. Test Data Input--A test data serial signal for test instructions and data. TDI is sampled on the rising edge of TCK and has an internal pull-up resistor. Test Data Output--A test data serial signal for test instructions and data. TDO can be tri-stated. The signal is actively driven in the shift-IR and shift-DR controller states and changes on the falling edge of TCK. Test Mode Select--Sequences the test controller's state machine, is sampled on the rising edge of TCK, and has an internal pull-up resistor. Test Reset--Asynchronously initializes the test controller, has an internal pull-up resistor, and must be asserted after power up.
TMS TRST
Input Input
1.8 Reserved Signals
Table 1-9. Reserved Signals
Signal Name
TEST
Type
Input
Signal Description
Test Used for manufacturing testing. You must connect this pin to GND.
1-22
Chapter 2
Specifications
2.1 Introduction
This document contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications. For additional information, see the MSC8102 User's Manual and MSC8102 Reference Manual. Note: The MSC8102 electrical specifications are preliminary and many are from design simulations. These specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized specifications will be published after thorough characterization and device qualifications have been completed.
2-1
Maximum Ratings
2.2 Maximum Ratings
CAUTION
This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, normal precautions should be taken to avoid exceeding maximum voltage ratings. Reliability is enhanced if unused inputs are tied to an appropriate logic voltage level (for example, either GND or VDD).
In calculating timing requirements, adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum. A maximum specification is calculated using a worst case variation of process parameter values in one direction. The minimum specification is calculated using the worst case for the same parameters in the opposite direction. Therefore, a "maximum" value for a specification never occurs in the same device with a "minimum" value for another specification; adding a maximum to a minimum represents a condition that can never exist. Table 2-1 describes the maximum electrical ratings for the MSC8102. Table 2-1. Absolute Maximum Ratings
Rating
Core supply voltage PLL supply voltage I/O supply voltage Input voltage Maximum operating temperature range Storage temperature range Notes: 1. 2. 3.
Symbol
VDD VCCSYN VDDH VIN TJ TSTG
Value
-0.2 to 2.1 -0.2 to 2.1 -0.2 to 4.0 (GND - 0.2) to 4.0 TBD -55 to +150
Unit
V V V V C C
Functional operating conditions are given in Table 2-2. Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond the listed limits may affect device reliability or cause permanent damage. Section 4.1, Thermal Design Considerations, on page 1 includes a formula for computing the chip junction temperature (TJ ).
2-2
Recommended Operating Conditions
2.3 Recommended Operating Conditions
Table 2-2 lists recommended operating conditions. Proper device operation outside of these conditions is not guaranteed. Table 2-2. Recommended Operating Conditions
Rating
Core supply voltage PLL supply voltage I/O supply voltage Input voltage Operating temperature range
Symbol
VDD VCCSYN VDDH VIN TJ
Value
1.55 to 1.7 1.55 to 1.7 3.135 to 3.465 -0.2 to VDDH+0.2 250 MHz: -40 to 105 275 MHz: TBD
Unit
V V V V C
2.4 Thermal Characteristics
Table 2-3 describes thermal characteristics of the MSC8102 for the FC-CBGA (HCTE) package. Table 2-3. Thermal Characteristics for FC-CBGA (HCTE) Package
FC-CBGA (HCTE) 20 Characteristic
Junction-to-ambient1, 2 Junction-to-ambient, four-layer board Junction-to-board (bottom)4 Notes: 1. 2. 3. 4. 5.
1, 3
x 20 mm5
200 ft/min (1 m/s) airflow
20.7 13.1
Symbol
RJA or JA RJA or JA RJB or JB
Natural Convection
28.5 16.6 7.5
100 ft/min (.5 m/s) airflow
23.7 14.3
Unit
C/W C/W C/W
Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. Per SEMI G38-87 and EIA/JESD51-2 with the single layer (1s) board horizontal. Per JESD51-6 with the board horizontal. Thermal resistance between the die and the printed circuit board per JESD 51-8. Board temperature is measured on the top surface of the board near the package. Values listed are based on simulations. Final values will be released when testing is complete.
Note:
Pre-production MSC8102 devices use an FC-PBGA package. The thermal characteristics for this package have not yet been determined.
Section 4.1, Thermal Design Considerations provides a more detailed explanation of these characteristics.
2-3
DC Electrical Characteristics
2.5 DC Electrical Characteristics
This section describes the DC electrical characteristics for the MSC8102. The measurements in Table 2-4 assume the following system conditions: * * * * TA = 0-70 C V DD = 1.55-1.7 VDC V DDH = 3.3 V 5% VDC GND = 0 VDC The leakage current is measured for nominal VDDH and VDD or both VDDH and VDD must vary in the same direction (for example, both VDDH and VDD vary by +2 percent or both vary by -2 percent). Table 2-4. DC Electrical Characteristics
Characteristic
Input high voltage, all inputs except CLKIN Input low voltage CLKIN input high voltage CLKIN input low voltage Input leakage current, VIN = VDDH Tri-state (high impedance off state) leakage current, VIN = VDDH Signal low input current, VIL = 0.4 V Signal high input current, VIH = 2.0 V Output high voltage, IOH = -2 mA, except open drain pins Output low voltage, IOL= 3.2 mA Core power at * 250 MHz * 275 MHz Peripherals power at * 250 MHz * 275 MHz I/O power at * 83 MHz * 92 MHz Note:
Note:
Symbol
VIH VIL V IHC VILC IIN IOZ IL IH VOH V OL PCORE
Min
2.0 GND 2.4 GND -- -- TBD TBD 2.0 -- -- --
Typical
3.0 0 3.0 0 TBD TBD TBD TBD 3.0 0 1.84 TBD TBD TBD TBD TBD
Max
3.465 0.4 3.465 0.4 TBD TBD TBD TBD -- 0.4 -- -- -- -- -- --
Unit
V V V V A A A A V V W W W W W W
PPERIPH -- -- PI/O -- --
Power consumption was determined from the average current draw at 1.6 V core voltage when running a 4-core EFR pattern.
2-4
AC Timings
2.6 AC Timings
2.6.1 Load Assumptions
The following sections include illustrations and tables of clock diagrams, signals, and parallel I/O outputs and inputs. AC timings are based on a 50 pF load, except where noted otherwise, and a 50 transmission line. For any additional pF, add 0.07 ns for the delay and take the RC delay into consideration.
2.6.2 Clock and Timing Signals
The following sections include a description of clock signal characteristics. Table 2-5. System Clock Parameters
Characteristic
Phase jitter between CLKOUT and DLLIN CLKIN frequency CLKIN slope DLLIN slope CLKOUT frequency jitter Delay between CLKOUT and DLLIN Note:
Minimum
-- 36 -- -- -- --
Maximum
0.5 75 5 2 (0.01 x CLKOUT) + CLKIN jitter 5
Unit
ns MHz ns ns ns ns
Low CLKIN frequency causes poor PLL performance. Choose a CLKIN frequency high enough to keep the frequency after predivider (SPLLMFCLK) higher than 18 MHz
Table 2-6 shows the maximum frequency values for internal (Core, Reference, and DSI) and external (CLKOUT) clocks. The user must ensure that maximum frequency values are not exceeded. Table 2-6. Maximum Frequencies
Characteristic
Core Frequency Reference Frequency (REFCLK) DSI Clock Frequency (HCLKIN) External Clock Output Frequency (CLKOUT) Note: The REFCLK is CLKOUT.
Maximum in MHz
250/275 83.3/91.7 if REFCLK 70 MHz, HCLKIN = CLKOUT if REFCLK > 70 MHz, HCLKIN = 70 MHz 83.3/91.7
2-5
AC Timings
Table 2-7. Clock Operation
250 MHz Device Characteristics
CLKIN1 * Frequency * Cycle time DLLIN 1 * Frequency * Cycle time Reference Clock (REFCLK) * Frequency * Cycle time Output Clock (CLKOUT) * Frequency * Cycle time SC140 core clock * Frequency * Cycle time Notes: 1. 2.
275 MHz Device Min
36 MHz 13.3 ns 33.3 MHz 13.3 ns 33.3 MHz 10.9 ns 33.3 MHz 10.9 ns 166.7 MHz 3.6 ns
Symbol Min
FCLKIN TCLKIN FDLLIN TDLLIN FREFCLK TREFCLK FCLKOUT TCLKOUT FCORE TCORE 36 MHz 13.3 ns 33.3 MHz 13.3 ns 33.3 MHz 12 ns 33.3 MHz 12 ns 166.7 MHz 4 ns
Max
75 MHz 28 ns 75 MHz 30 ns 83.3 MHz 30 ns 83.3 MHz 30 ns 250 MHz 6 ns
Max
75 MHz 28 ns 75 MHz 30 ns 91.7 MHz 30 ns 91.7 MHz 30 ns 275 MHz 6 ns
The rise and fall time of external clocks should be 5 ns maximum Measured at 50 percent of the input transition.
2.6.3 Reset Timing
The MSC8102 has several inputs to the reset logic: * * * * * * Power-on reset (PORESET) External hard reset (HRESET) External soft reset (SRESET) Software watchdog reset Bus monitor reset Host reset command through JTAG
All MSC8102 reset sources are fed into the reset controller, which takes different actions depending on the source of the reset. The reset status register indicates the most recent sources to cause a reset. Table 2-8 describes the reset sources. Table 2-8. Reset Sources
Name
Power-on reset (PORESET)
Direction
Input
Description
Initiates the power-on reset flow that resets the MSC8102 and configures various attributes of the MSC8102. On PORESET, the entire MSC8102 device is reset. SPLL and DLL states are reset, HRESET and SRESET are driven, the SC140 extended cores are reset, and system configuration is sampled. The clock mode (MODCK bits), reset configuration mode, boot mode, Chip ID, and use of either a DSI 64 bits port or a System Bus 64 bits port are configured only when PORESET is asserted. Initiates the hard reset flow that configures various attributes of the MSC8102. While HRESET is asserted, SRESET is also asserted. HRESET is an open-drain pin. Upon hard reset, HRESET and SRESET are driven, the SC140 extended cores are reset, and system configuration is sampled. The most configurable features are reconfigure. These features are defined in the 32-bit hard reset configuration word described in Hard Reset Configuration Word section of the Reset chapter in the MSC8102 Reference Manual.
External Hard reset (HRESET)
Input/ Output
2-6
AC Timings
Table 2-8. Reset Sources
Name
External Soft reset (SRESET) Software watchdog reset Bus monitor reset Host reset command through the TAP
Direction
Input/ Output
Description
Initiates the soft reset flow. The MSC8102 detects an external assertion of SRESET only if it occurs while the MSC8102 is not asserting reset. SRESET is an open-drain pin. Upon soft reset, SRESET is driven, the SC140 extended cores are reset, and system configuration is maintained. When the MSC8102 watchdog count reaches zero, a software watchdog reset is signalled. The enabled software watchdog event then generates an internal hard reset sequence. When the MSC8102 bus monitor count reaches zero, a bus monitor hard reset is asserted. The enabled bus monitor event then generates an internal hard reset sequence. When a host reset command is written through the Test Access Port (TAP), the TAP logic asserts the soft reset signal and an internal soft reset sequence is generated.
Internal
Internal
Internal
Table 2-9 summarizes the reset actions that occur as a result of the different reset sources. Table 2-9. Reset Actions for Each Reset Source
Power-On Reset (PORESET) Reset Action/Reset Source External only Hard Reset (HRESET) External or Internal (Software Watchdog or Bus Monitor)
No No No Yes Yes Yes Yes
Soft Reset (SRESET)
Extern al
JTAG Command: EXTEST, CLAMP, or HIGHZ
No No No No No No Yes
Configuration Pins Sampled (Refer to Section 2.6.3.1 for details). SPLL and DLL States Reset System Reset Configuration write through the DSI System Reset Configuration write though the System Bus HRESET Driven SIU Registers reset IPBus Modules Reset (TDM, UART, Timers, DSI, IPBus Master, GIC, HS, and GPIO) SRESET Driven SC140 Extended Cores Reset MQBS Reset
Yes Yes Yes Yes Yes Yes Yes
No No No No No No Yes
Yes Yes Yes
Yes Yes Yes
Yes Yes Yes
Depends on command Yes Yes
2-7
AC Timings
2.6.3.1 Power-On Reset (PORESET) Pin
Asserting PORESET initiates the power-on reset flow. PORESET must be asserted externally for at least 16 CLKIN cycles after external power to the MSC8102 reaches at least 2/3 VDD.
2.6.3.2 Reset Configuration
The MSC8102 has two mechanisms for writing the reset configuration: * Through the direct slave interface (DSI), or * Through the system bus When reset configuration written through the system bus, the MSC8102 uses as a configuration master or as a configuration slave. If a configuration slave is selected, but no special configuration word is written, a default configuration word is applied. Fourteen signal levels (see Chapter 1 for signal description details) are sampled on PORESET deassertion to define the Reset Configuration Mode and boot and operating conditions: * * * * * * * *
RSTCONF CNFGS DSISYNC DSI64 CHIP_ID[0-3] BM[0-2] SWTE MODCK[1-2]
2.6.3.3 Reset Timing Tables
Table 2-10 and Figure 2-1 describe the reset timing for a reset configuration write through the direct slave interface (DSI) or through the system bus. Table 2-10. Timing for a Reset Configuration Write through the DSI or System Bus
No.
1
Characteristics
Required external PORESET duration minimum * CLKIN = 18 MHz * CLKIN = 75 MHz Delay from deassertion of external PORESET to deassertion of internal PORESET * CLKIN = 18 MHz * CLKIN = 75 MHz Delay from de-assertion of internal PORESET to SPLL lock * CLKIN = 18 MHz * CLKIN = 75 MHz Delay from SPLL lock to DLL lock. * DLL enabled REFCLK = 18 Mhz REFCLK = 75 Mhz * DLL disabled
Expression
16 / CLKIN
Min
Max
--
Unit
ns
888.8 213.3 1024 / CLKIN 58.89 13.65 800 / (CLKIN/PDF) (pre-division factor) 44.4 32.0 s s s s
2
3
4
3073 / REFCLK 170.72 40.97 0.0 s s s
--
2-8
AC Timings
Table 2-10. Timing for a Reset Configuration Write through the DSI or System Bus
No.
5 * *
Characteristics
Delay from SPLL and DLL lock to HRESET de-assertion DLL enabled REFCLK = 18 Mhz REFCLK = 75 Mhz DLL disabled REFCLK = 18 Mhz REFCLK = 75 Mhz
Expression
Min
Max
Unit
3585 / REFCLK 199.17 47.5 512 / REFCLK 28.4 6.83 s s s s
*
6
Delay from SPLL and DLL lock to SRESET de-assertion * DLL enabled REFCLK = 18 Mhz REFCLK = 75 Mhz * DLL disabled REFCLK = 18 Mhz REFCLK = 75 Mhz
3588 / REFCLK 199.33 47.84 515 / REFCLK 28.61 6.87 s s s s
1
RSTCONF, CNFGS, DSISYNC, DSI64 CHIP_ID[0-3], BM[0-2], SWTE, MODCK[1-2] pins are sampled Host programs Reset Configuration Word SPLL and DLL are locked (no external indication)
PORESET Input
PORESET Internal
1+2
HRESET Output (I/O)
2
MODCK[3-5], DLLDIS bits are ready for SPLL.
3+4
SRESET Output (I/O)
SPLL and DLL Reset configuration write locking period. sequence occurs during this When DLL is disabled, period. reset period is shortened by 3073 bus clocks.
5 6
Figure 2-1. Timing Diagram for a Reset Configuration Write
2-9
AC Timings
2.6.4 System Bus Access Timing
2.6.4.1 Core Data Transfers
Generally, all MSC8102 bus and system output signals are driven from the rising edge of the reference clock (REFCLK). The REFCLK is either the DLLIN signal or, if DLL is disabled, the CLKOUT signal. Memory controller signals, however, trigger on four points within a REFCLK cycle. Each cycle is divided by four internal ticks: T1, T2, T3, and T4. T1 always occurs at the rising edge of REFCLK (and T3 at the falling edge), as Figure 2-2 shows. Figure 2-2 is a graphical representation of the internal ticks.
REFCLK T1 T2 T3 T4
Figure 2-2. Internal Tick Spacing for Memory Controller Signals The UPM machine and GPCM machine outputs change on the internal tick determined by the memory controller programming, the AC specifications are relative to the internal tick. SDRAM machine outputs change only on the REFCLK rising edge. Table 2-11. AC Timing for SIU Inputs in Non-Pipelined Mode
No.
10 11 12 13 14 15 16 Hold time for all signals after REFCLK rising edge AACK/ARTRY/TA/TEA/DBG/BG/BR/PSDVAL setup time before REFCLK rising edge Data bus setup time before REFCLK rising edge in Normal mode Data bus setup time before REFCLK rising edge in ECC and PARITY modes DP setup time before REFCLK rising edge Address bus/TT[0-4]/TC[0-2]/TBST/TSIZ[0-3]/GBL setup time before REFCLK rising edge Setup time before REFCLK rising edge for all other pins 1. 2.
Characteristic
Value Units
0.5 5 4.5 6 6 4 4 ns ns ns ns ns ns ns
Notes:
Values are measured from the TTL signal level (0.8 or 2.0 V) relative to the REFCLK rising edge. SIU inputs are for the normal configuration (SIUBCR[EXDD] = 0--which gives an extra cycle for address inputs. When SIUBCR[EXDD] = 1, address setup time is 10 ns, requiring a maximum bus frequency of 50 MHz.
Table 2-12. AC Timing for SIU Inputs in Pipelined Mode
No.
10 11 12 13 14 15 16 Hold time for all signals after REFCLK rising edge AACK/ARTRY/TA/TEA/DBG/BG/BR setup time before REFCLK rising edge Data bus setup time before REFCLK rising edge in Normal mode Data bus setup time before REFCLK rising edge in ECC and Parity modes DP setup time before REFCLK rising edge Address bus/TT[0-4]/TC[0-2]/TBST/TSIZ[0-3]/GBL setup time before REFCLK rising edge Setup time before REFCLK rising edge for all other pins 1. 2.
Characteristic
Value Units
0.5 ns ns ns ns ns ns ns
4.5 3 5.5 5
3.5
3
Notes:
Values are measured from the TTL signal level (0.8 or 2.0 V) relative to the REFCLK rising edge. SIU inputs are for the normal configuration (SIUBCR[EXDD] = 0--which gives an extra cycle for address inputs. When SIUBCR[EXDD] = 1, address setup time is 10 ns, requiring a maximum bus frequency of 50 MHz.
2-10
AC Timings
Table 2-13. AC Timing for SIU Outputs for 30 pF in Non-Pipelined Mode
No.
31
Characteristic
PSDVAL/TEA/TA delay from REFCLK rising edge
Minimum Maximum
0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 7.5 81 8 7.5 7.5 6.5 6.5 6.5
Units
ns ns ns ns ns ns ns ns
32a Address bus/TT[0-4]/TC[0-2]/TBST/TSIZ[0-3]/GBL delay from REFCLK rising edge 32b BADDR delay from REFCLK rising edge 33a Data bus delay from REFCLK rising edge 33b DP delay from REFCLK rising edge 34 35 36 Memory controller signals/ALE delay from REFCLK rising edge DBG/BR/ABB/CS delay from REFCLK rising edge Delay from REFCLK rising edge for all other signals 1. 2.
Notes:
In 60x-compatible mode with SIUBCR[EBM] = 1. Values are measured from the 1.4 V level of the REFCLK rising edge to the TTL signal level (0.8 or 2 V)
Table 2-14. AC Timing for SIU Outputs for 30pF in Pipelined Mode
No.
31
Characteristic
PSDVAL/TEA/TA delay from REFCLK rising edge
Minimum Maximum
0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 7 62 6 6 7 6 6.5 6.5
Units
ns ns ns ns ns ns ns ns
32a Address bus/TT[0-4]/TC[0-2]/TBST/TSIZ[0-3]/GBL delay from REFCLK rising edge 32b BADDR delay from REFCLK rising edge 33a Data bus delay from REFCLK rising edge 33b DP delay from REFCLK rising edge 34 35 36 Memory controller signals/ALE delay from REFCLK rising edge DBG/BR/ABB/CS delay from REFCLK rising edge Delay from REFCLK rising edge for all other signals 1.
Notes:
2. 3.
The maximum bus frequency depends on the mode: * In 60x-compatible mode connected to another MSC8102 device, the frequency is determined by adding the input and output longest timing values, which results in a frequency of 80 MHz. * In single-master mode, the frequency depends on the timing of the devices connected to the MSC8102. In single master mode with SIUBCR[EBM] = 0. Values are measured from the 1.4 V level of the REFCLK rising edge to the TTL signal level (0.8 or 2 V)
Table 2-15. AC Timing for SIU Outputs for 50 pF in Non-Pipelined Mode
No.
31
Characteristic
PSDVAL/TEA/TA delay from REFCLK rising edge
Minimum Maximum
0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 9.5 10 8.5 9.5 9.5 8 8.5 8
Units
ns ns ns ns ns ns ns ns
32a Address bus/TT[0-4]/TC[0-2]/TBST/TSIZ[0-3]/GBL delay from REFCLK rising edge 32b BADDR delay from REFCLK rising edge 33a Data bus delay from REFCLK rising edge 33b DP delay from REFCLK rising edge 34 35 36 Note: Memory controller signals/ALE delay from REFCLK rising edge DBG/BR/ABB/CS delay from REFCLK rising edge Delay from REFCLK rising edge for all other signals
Values are measured from the 1.4 V level of the REFCLK rising edge to the TTL signal level (0.8 or 2 V)
2-11
AC Timings
Table 2-16. AC Timing for SIU Outputs for 50 pF in Pipelined Mode
No.
31
Characteristic
PSDVAL/TEA/TA delay from REFCLK rising edge
Minimum Maximum
0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 9 8 8 8 9.5 8 8.5 8
Units
ns ns ns ns ns ns ns ns
32a Address bus/TT[0-4]/TC[0-2]/TBST/TSIZ[0-3]/GBL delay from REFCLK rising edge 32b BADDR delay from REFCLK rising edge 33a Data bus delay from REFCLK rising edge 33b DP delay from REFCLK rising edge 34 35 36 Note: Memory controller signals/ALE delay from REFCLK rising edge DBG/BR/ABB/CS delay from REFCLK rising edge Delay from REFCLK rising edge for all other signals
Values are measured from the 1.4 V level of the REFCLK rising edge to the TTL signal level (0.8 or 2 V)
REFCLK 10 AACK/ARTRY/TA/TEA/DBG/BG/BR/PSDVAL inputs 11
10 12 Data bus inputs--normal mode 10 Data bus inputs--ECC and parity modes DP inputs Address bus/TT[0-4]/TC[0-2]/TBST/TSIZ[0-3]/GBL inputs All other inputs PSDVAL/TEA/TA outputs Address bus/TT[0-4]/TC[0-2]/TBST/TSIZ[0-3]/GBL outputs BADDR 32a 13 14 15 16 31 10
32b 33a
Data bus outputs DP outputs
33b
34 Memory controller/ALE signals 35 DBG/BR/ABB/CS 36 All other normal mode outputs
Figure 2-3. Bus Signal Timing
2-12
AC Timings
2.6.4.2 DMA Data Transfers
Table 2-17 describes the DMA signal timing. Table 2-17. DMA Signals
No.
37 38 39 40 41
Characteristic
DREQ setup time before falling edge of REFCLK DREQ hold time after falling edge of REFCLK DONE setup time before falling edge of REFCLK DONE hold time after falling edge of REFCLK DACK/DRACK/DONE delay after REFCLK rising edge
Minimum Maximum
6 0.5 9 0.5 0.5 -- -- -- -- 9
Units
ns ns ns ns ns
The DREQ signal is synchronized with REFCLK. To achieve fast response, a synchronized peripheral should assert DREQ according to the timings in Table 2-17. Figure 2-4 shows synchronous peripheral
interaction.
REFCLK 38 37 DREQ 40 39 DONE 41 DACK/DONE/DRACK
Figure 2-4. DMA Signals
2-13
AC Timings
2.6.5 DSI Timing
The timings in the following sections are based on a 30 pF capacitive load. See Section 2.6.1, Load Assumptions, on page 5 for more details.
2.6.5.1 DSI Asynchronous Mode
Table 2-18. DSI Asynchronous Mode Timing
No.
100 101 102 Attributes1 Attributes1
Characteristics
setup time before strobe (HWBS[n]) assertion hold time after data strobe deassertion width2
Min
3.6 2.4
Max
-- -- --
Unit
ns ns
Read/Write data strobe deassertion * DCR[HTAAD] = 1 -- Consecutive access to the same DSI -- Different device with DCR[HTADT] = 01 -- Different device with DCR[HTADT] = 10 -- Different device with DCR[HTADT] = 11 * DCR[HTAAD] = 0 Read data strobe deassertion to output data high impedance Read data strobe assertion to output data active from high impedance Output data hold time after read data strobe deassertion Read/Write data strobe assertion to HTA active from high impedance Output data valid to HTA assertion Read/Write data strobe assertion to HTA valid Read/Write data strobe deassertion to output HTA high impedance. (DCR[HTAAD] = 0, HTA at end of access released at logic 0) Read/Write data strobe deassertion to output HTA deassertion. (DCR[HTAAD] = 1, HTA at end of access released at logic 1) Read/Write data strobe deassertion to output HTA high impedance. (DCR[HTAAD] = 1, HTA at end of access released at logic 1 * DCR[HTADT] = 01 * DCR[HTADT] = 10 * DCR[HTADT] = 11 Read/Write data strobe assertion width Host data input setup time before write data strobe deassertion Host data input hold time after write data strobe deassertion 1.
1.8 + TREFCLK 5 + TREFCLK 5 + (1.5 x TREFCLK) 5 + (2.5 x TREFCLK) 1.8 + TREFCLK -- 3.8 2.2 3.9 1 -- -- -- -- 5 + TREFCLK 5 + (1.5 x TREFCLK) 5 + (2.5 x TREFCLK) 1.8 + TREFCLK 2 1.3 -- -- -- 7.8 -- -- -- -- 9.8 6.5 9.2
ns ns ns ns ns ns ns ns ns ns ns ns ns
103 104 105 106 107 108 109 110 111
ns ns ns ns ns ns
112 201 202
Notes:
"Attributes" refers to the following signals: HCS, HA[11-29], HCID[0-4], HDST, HRW, HRDS, and HWBSn.
2-14
AC Timings
Figure 2-5 shows DSI Asynchronous Read signals timing.
HCS HA[11-29] HCID[0-4] HDST HRW1 HWBSn 2
100
101
112 HDBSn1 HRDS2 102 103
107 104 HD[0-63] 106
105
109
HTA3 108 110
HTA4
111 Notes: 1. 2. 3. 4. Used for Single Strobe mode access. Used for Dual Strobe mode access. HTA released at logic 0 (DCR[HTAAD] = 0) at end of access; used with pull-down implementation. HTA released at logic 1 (DCR[HTAAD] = 1) at end of access; used with pull-up implementation.
Figure 2-5. Asynchronous Single and Dual Modes Read Timing Diagram
2-15
AC Timings
Figure 2-6 shows DSI Asynchronous Write signals timing.
HCS HA[11-29] HCID[0-4] HDST HRW1 HRDS2
100
101
112 HDBSn1 HWBSn2 201 202 HD[0-63] 109
102
106 HTA3
108
110
HTA4
111 Notes: 1. 2. 3. 4. Used for Single Strobe mode access. Used for Dual Strobe mode access. HTA released at logic 0 (DCR[HTAAD] = 0) at end of access; used with pull-down implementation. HTA released at logic 1 (DCR[HTAAD] = 1) at end of access; used with pull-up implementation.
Figure 2-6. Asynchronous Single and Dual Modes Write Timing Diagram
2-16
AC Timings
Figure 2-7 shows DSI Asynchronous Broadcast Write signals timing.
HCS HA[11-29] HCID[0-4] HDST HRW1 HRDS2
100
101
112 HDBSn HWBSn2 201 202 HD[0-63] 109
1
102
106 HTA3
108
110
HTA4
111 Notes: 1. 2. 3. 4. Used for Single Strobe mode access. Used for Dual Strobe mode access. HTA released at logic 0 (DCR[HTAAD] = 0) at end of access; used with pull-down implementation. HTA released at logic 1 (DCR[HTAAD] = 1) at end of access; used with pull-up implementation.
Figure 2-7. Asynchronous Broadcast Write Timing Diagram
2-17
AC Timings
2.6.5.2 DSI Synchronous Mode
Table 2-19. DSI Inputs--Synchronous Mode
Number
120 121 122 123 124 125 126 Notes: 1.
Characteristic
HCLKIN Cycle Time
1
Expression
HTC (0.5 0.1) x HTC (0.5 0.1) x HTC -- -- -- --
Minimum
14.3 5.7 5.7 2.7 4.2 1.5 2.2
Maximum
55.6 33.3 33.3 -- -- -- --
Units
ns ns ns ns ns ns ns
HCLKIN High Pulse Width HCLKIN Low Pulse Width HD[0-63], HA[11-29] inputs Setup time HCID[0-4] inputs Setup time All other inputs Setup time All inputs Hold time
Values are based on a frequency range of 18-70 MHz.
Table 2-20. DSI Outputs--Synchronous Mode
Number
127 128 129 130 131 132 133 134
Characteristic
HCLKIN High to HD[0-63] output active HCLKIN High to HD[0-63] output valid HD[0-63] output Hold time HCLKIN High to HD[0-63] output high impedance HCLKIN High to HTA output active HCLKIN High to HTA output valid HTA output Hold time HCLKIN High to HTA high impedance
Minimum
0 -- 1.6 -- 0 -- 1.7 --
Maximum
-- 8.6 -- 6.2 -- 7.4 -- 4.4
Units
120 122
HCLKIN 123 HD[0-63], HA[11-29] input signals 124 HCID[0-4] input signals 125 All other input signals 128
121 126
126
126 130 129 ~~ ~~
127 HD[0-63] output signals
132 131 ~ ~ HTA output signal
134 133
Figure 2-8. DSI Synchronous Mode Signals Timing Diagram 2-18
AC Timings
2.6.6 TDM Timing
.
Table 2-21. TDM Timing
Number
300 301 302 303 304 305 306 307 308 309 310 Notes: 1. 2.
Characteristic
TDMxRCLK/TDMxTCLK TDMxRCLK/TDMxTCLK High Pulse Width TDMxRCLK/TDMxTCLK Low Pulse Width TDM receive all input Setup time TDM receive all input Hold time TDMxTCLK High to TDmXTDAT output active2 TDMxTCLK High to TDMXTDAT output valid2 All output hold time2 TDMxTCLK High to TDmXTDAT output high impedance2 TDMxTCLK High to TDMXTSYN output valid2 TDMxTSYN output hold time2
Expression
TC1 (0.5 0.1) x TC (0.5 0.1) x TC
Minimum Maximum
20 8 8 2.5 1 4 -- 5.2 -- -- 5.2 111 66.7 66.7 -- -- -- 14 -- 10 13.5 --
Units
ns ns ns ns ns ns ns ns ns ns ns
Values are based on a frequency range of 9-50 MHz. Values are based on 30 pF capacitive load.
300 301 TDMxRCLK 304 303 TDMxRDAT 304 303 TDMxRSYN 302
Figure 2-9. TDM Inputs Signals
300 301 TDMxTCLK 306 302 308
~ ~
309
305 TDMxTDAT
307
TDMxTSYN
Figure 2-10. TDM Output Signals 2-19
~ ~
310
AC Timings
2.6.7 UART Timing
Table 2-22. UART Timing
No.
400 401 402
Characteristics
URXD and UTXD inputs high/low duration URXD and UTXD inputs rise/fall time UTXD output rise/fall time
Expression
16 x TREFCLK
Min
160.0
Max
-- 5 5
Unit
ns ns ns
401
401
UTXD, URXD inputs 400 400
Figure 2-11. UART Input Timing
402
402
UTXD output
Figure 2-12. UART Output Timing
2-20
AC Timings
2.6.8 Timer Timing
500
501
502
TIMERx (Input)
503
TIMERx (Output)
Figure 2-13. Timer Timing Table 2-23. Timer Timing
92 MHz No.
500 501 502 503
Characteristics Min.
TIMERx frequency TIMERx Input high period TIMERx Output low period TIMERx Propagations delay from its clock input 10.9 4 4 5.8
Unit Max
-- -- -- 12.3 ns ns ns ns
2-21
AC Timings
2.6.9 GPIO Timing
Table 2-24. GPIO Timing
92 MHz No.
601 602 603 604 605
Characteristics Min
REFCLK edge to GPIO out valid (GPIO out delay time) REFCLK edge to GPIO out not valid (GPIO out hold time) REFCLK edge to high impedance on GPIO out GPIO in valid to REFCLK edge (GPIO in setup time) REFCLK edge to GPIO in not valid (GPIO in hold time) -- 2.5 -- 4.5 0.5
Unit Max
8.5 -- 3 -- -- ns ns ns ns ns
REFCLK (Output)
601 603 602 High Impedance
GPIO (Output)
604 GPIO (Input)
605
Valid
Figure 2-14. GPIO Timing
2-22
AC Timings
2.6.10 EE Signals
Table 2-25. EE Pin Timing
Number
65 66 Notes: 1. 2. 3.
Characteristics
EE pins as inputs EE pins as outputs
Type
Asynchronous Synchronous to Core clock
Minimum
4 core clock periods 1 core clock period
The core clock is the SC140 core clock. The ratio between the core clock and CLKOUT is configured during power-on-reset. Direction of the EE pins is configured in the EE_CTRL register of the EOnCE (See the SC140 Core Reference Manual and the MSC8102 Reference Manual for details). Refer to Table 1-4 on page 1-6 for detailed information about EE pin functionality.
Figure 2-15 shows the signal behavior of the EE pins.
65 EE in
66 EE out
Figure 2-15. EE Pins Timing
2-23
AC Timings
2.6.11 JTAG Signals
Table 2-26. JTAG Timing
All frequencies No. Characteristics1,2 Min
700 701 702 703 704 705 706 707 708 709 710 711 712 713 Notes: TCK frequency of operation (1/(TC x 3); maximum 22 MHz) TCK cycle time in Crystal mode TCK clock pulse width measured at VM = 1.6 V TCK rise and fall times Boundary scan input data set-up time Boundary scan input data hold time TCK low to output data valid TCK low to output high impedance TMS, TDI data set-up time TMS, TDI data hold time TCK low to TDO data valid TCK low to TDO high impedance TRST assert time TRST set-up time to TCK low 1. 2. 0.0 45.0 20.0 0.0 5.0 24.0 0.0 0.0 5.0 25.0 0.0 0.0 100.0 40.0
Unit Max
22.0 -- -- 3.0 -- -- 40.0 40.0 -- -- 44.0 44.0 -- -- MHz ns ns ns ns ns ns ns ns ns ns ns ns ns
VDDH = 3.3 V 0.3 V; TJ = TBD, CL = 50 pF All timings apply to OnCE module data transfers as the OnCE module uses the JTAG port as an interface.
701 702 TCK (Input) VIH 703 VM VIL 703 702 VM
Figure 2-16. Test Clock Input Timing Diagram
2-24
AC Timings
TCK (Input)
VIH VIL 704 705
Data Inputs 706 Data Outputs 707 Data Outputs
Input Data Valid
Output Data Valid
Figure 2-17. Boundary Scan (JTAG) Timing Diagram
VIH V IL 708 TDI TMS (Input) 710 TDO (Output) 711 TDO (Output) Output Data Valid Input Data Valid 709
TCK (Input)
Figure 2-18. Test Access Port Timing Diagram
TCK (Input) 713 TRST (Input) 712
Figure 2-19. TRST Timing Diagram
2-25
AC Timings
2-26
Chapter 3
Packaging
3.1 Pinout and Package Information
This sections provides information about the MSC8102 package, including diagrams of the package pinouts and tables showing how the signals discussed in Chapter 1, Signal/Connection Descriptions are allocated. The MSC8102 is available in a 431-pin High Temperature Coefficient for Expansion Flip Chip-Ceramic Ball Grid Array (FC-CBGA (HCTE)) and will be used for qualified production parts. Some pre-production MSC8102 devices are provided in a 431-pin Flip Chip-Plastic Ball Grid Array (FC-PBGA) package that may include a copper lid.
3.2 FC-CBGA (HCTE) Package Description
Figure 3-1 and Figure 3-2 show top and bottom views of the FC-CBGA (HCTE) package, including pinouts. To conform to JDEC requirements, the package is based on a 23 x 23 position (20 x 20 mm) layout with the outside perimeter depopulated. Therefore, ball position numbering starts with B2. Signal names shown in the figures are typically the signal assigned after reset. Signals that are only used during power-on reset (SWTE, DSISYNC, DSI64, MODCK[1-2], CNFGS, and CHIP_ID[0-3]) are not shown in these figures if there is another signal assigned to the pin after reset. Also, there are several signals that are designated as IRQ lines immediately after reset, but represent duplicate IRQ lines that should be reconfigured by the user. To represent these signals uniquely in the figures, the second functions (BADDR[29-31], DP[1-7], and INT_OUT) are used. Table 3-1 lists the MSC8102 signals alphabetically by signal name. Connections with multiple names are listed individually by each name. Signals with programmable polarity are shown both as signals which are asserted low (default) and high (that is, NAME/NAME). Table 3-2 lists the signals numerically by pin number. Each pin number is listed once with the various signals that are multiplexed to it. For simplicity, signals with programmable polarity are shown in this table only with their default name (asserted low). Note: Pre-production MSC8102 devices are shipped with the FC-PBGA package. It has the same pinout as the FC-CBGA package.
3-1
FC-CBGA (HCTE) Package Description
Top View
2
B
3
VDD
4
GND
5
GND
6
NMI_ OUT
7
GND
8
VDD
9
GND
10
VDD
11
GND
12
VDD
13
GND
14
VDD
15
GND
16
VDD
17
GND
18
VDD
19
GPIO0
20
VDD
21
VDD
22
GND
C
GND
VDD
TDO
S GPIO28 HCID1 RESET
GND
VDD
GND
VDD
GND
VDD
GND
GND
GPIO30 GPIO2
GPIO1
GPIO7
GPIO3
GPIO5
GPIO6
D
TDI
EE0
EE1
GND
VDDH
HCID2
HCID3
GND
VDD
GND
VDD
GND
VDD
VDD
GPIO31 GPIO29
VDDH
GPIO4
VDDH
GND
GPIO8
E
TCK
TRST
TMS
HRESET GPIO27 HCID0
GND
VDD
GND
VDD
GND
VDD
GND
GND
VDD
GND
GND
GPIO9 GPIO13 GPIO10 GPIO12
F
PO RESET
RST CONF
NMI
HA29
HA22
GND
VDD
VDD
VDD
GND
VDD
GND
VDD
GND
VDD
GPIO20 GPIO18 GPIO16 GPIO11 GPIO14 GPIO19
G
HA24
HA27
HA25
HA23
HA17
PWE0
VDD
VDD
BADDR 31
BM0
ABB
VDD
INT_ OUT
VDD
VDD
CS1
BCTL0 GPIO15
GND
GPIO17 GPIO22
H
HA20
HA28
VDD
HA19
TEST
PSD CAS PSDA MUX
PGTA
VDD
BM1
ARTRY
AACK
DBB
HTA
VDD
TT4
CS4
GPIO24 GPIO21
VDD
VDDH
A31
J
HA18
HA26
VDD
HA13
GND
BADDR 27
VDD
CLKIN
BM2
DBG
VDD
GND
VDD
TT3
PSDA10 BCTL1 GPIO23
GND
GPIO25
A30
K
HA15
HA21
HA16
PWE3
PWE1
POE
BADDR DLLIN 30
GND
GND
GND
GND CLKOUT
VDD
TT2
ALE
CS2
GND
A26
A29
A28
L
HA12
HA14
HA11
VDDH
VDDH
BADDR BADDR 28 29
GND
GND
GND
VDDH
GND
GND
CS3
VDDH
A27
A25
A22
M SC
HB RST
M
HD28
HD31
VDDH
GND
GND
GND
VDD
VDDH
GND
GND
VDDH
VDDH
VDDH
GND
VDDH
A24
A21
81 02
N
HD26
HD30
HD29
HD24
PWE2
VDDH
HWBS 0
HBCS
GND
GND
HRDS
BG
HCS
CS0
PSDWE GPIO26
A23
A20
P
HD20
HD27
HD25
HD23
HWBS 3 HWBS 6 HWBS 7
HWBS 2 HWBS 4 HWBS 5
HWBS HCLKIN 1
GND
GNDSYN VCCSYN
GND
GND
TA
BR
TEA
PSD VAL
DP0
VDDH
GND
A19
R
HD18
VDDH
GND
HD22
TSZ1
TSZ3
GBL
VDD
VDD
VDD
TT0
DP7
DP6
DP3
TS
DP2
A17
A18
A16
T
HD17
HD21
HD1
HD0
TSZ0
TSZ2
TBST
VDD
D16
TT1
D211
D23
DP5
DP4
DP1
D30
GND
A15
A14
U
HD16
HD19
HD2
D2
D3
D6
D8
D9
D11
D14
D15
D17
D19
D22
D25
D26
D28
D31
VDDH
A12
A13
V
HD3
VDDH
GND
D0
D1
D4
D5
D7
D10
D12
D13
D18
D20
GND
D24
D27
D29
A8
A9
A10
A11
W
HD6
HD5
HD4
GND
GND
VDDH
VDDH
GND
HDST1 HDST0
VDDH
GND
HD40
VDDH
HD33
VDDH
HD32
GND
GND
A7
A6
Y
HD7
HD15
VDDH
HD9
VDD
HD60
HD58
GND
VDDH
HD51
GND
VDDH
HD43
GND
VDDH
GND
HD37
HD34
VDDH
A4
A5
AA
VDD
HD14
HD12
HD10
HD63
HD59
GND
VDDH
HD54
HD52
VDDH
GND
VDDH
HD46
GND
HD42
HD38
HD35
A0
A2
A3
AB
GND
HD13
HD11
HD8
HD62
HD61
HD57
HD56
HD55
HD53
HD50
HD49
HD48
HD47
HD45
HD44
HD41
HD39
HD36
A1
VDD
Figure 3-1. MSC8102 High Temperature Coefficient for Expansion Flip Chip Ceramic Ball Grid Array (High CTE FC-CBGA), Top View
3-2
FC-CBGA (HCTE) Package Description
Bottom View
22
B GND
21
VDD
20
VDD
19
GPIO0
18
VDD
17
GND
16
VDD
15
GND
14
VDD
13
GND
12
VDD
11
GND
10
VDD
9
GND
8
VDD
7
GND
6
NMI_ OUT
5
GND
4
GND
3
VDD
2
C
GPIO6
GPIO5
GPIO3
GPIO7
GPIO1
GPIO2 GPIO30
GND
GND
VDD
GND
VDD
GND
VDD
GND
HCID1 GPIO28
S RESET
TDO
VDD
GND
D
GPIO8
GND
VDDH
GPIO4
VDDH
GPIO29 GPIO31
VDD
VDD
GND
VDD
GND
VDD
GND
HCID3
HCID2
VDDH
GND
EE1
EE0
TDI
E
GPIO12 GPIO10 GPIO13 GPIO9
GND
GND
VDD
GND
GND
VDD
GND
VDD
GND
VDD
GND
HCID0 GPIO27 HRESET
TMS
TRST
TCK
F GPIO19 GPIO14 GPIO11 GPIO16 GPIO18 GPIO20
VDD
GND
VDD
GND
VDD
GND
VDD
VDD
VDD
GND
HA22
HA29
NMI
RST CONF
PO RESET
G GPIO22 GPIO17
GND
GPIO15 BCTL0
CS1
VDD
VDD
INT_ OUT
VDD
ABB
BM0
BADDR 31
VDD
VDD
PWE0
HA17
HA23
HA25
HA27
HA24
H
A31
VDDH
VDD
GPIO21 GPIO24
CS4
TT4
VDD
HTA
DBB
AACK
ARTRY
BM1
VDD
PGTA
PSD CAS
TEST
HA19
VDD
HA28
HA20
J
A30
GPIO25
GND
GPIO23 BCTL1 PSDA10
TT3
VDD
GND
VDD
DBG
BM2
CLKIN
VDD
BADDR PSDA 27 MUX BADDR 30
GND
HA13
VDD
HA26
HA18
K
A28
A29
A26
GND
CS2
ALE
TT2
VDD
CLKOUT GND
GND
GND
GND
DLLIN
POE
PWE1
PWE3
HA16
HA21
HA15
L
A22
A25
A27
VDDH
CS3
GND
GND
VDDH
GND
GND
GND
BADDR BADDR 29 28
VDDH
VDDH
HA11
HA14
HA12
M
A21
A24
VDDH
GND
VDDH
VDDH
M SC
HB RST
VDDH
81 0
2
GND
GND
VDDH
VDD
GND
GND
GND
VDDH
HD31
HD28
N
A20
A23
GPIO26 PSDWE
CS0
HCS
BG
HRDS
GND
GND
HBCS
HWBS 0 HWBS 1
VDDH
PWE2
HD24
HD29
HD30
HD26
P
A19
GND
VDDH
DP0
PSD VAL
TEA
BR
TA
GND
GND
VCCSYN GND SYN
GND
HCLKIN
HWBS 2 HWBS 4 HWBS 5
HWBS 3 HWBS 6 HWBS 7
HD23
HD25
HD27
HD20
R
A16
A18
A17
DP2
TS
DP3
DP6
DP7
TT0
VDD
VDD
VDD
GBL
TSZ3
TSZ1
HD22
GND
VDDH
HD18
T
A14
A15
GND
D30
DP1
DP4
DP5
D23
D211
TT1
D16
VDD
TBST
TSZ2
TSZ0
HD0
HD1
HD21
HD17
U
A13
A12
VDDH
D31
D28
D26
D25
D22
D19
D17
D15
D14
D11
D9
D8
D6
D3
D2
HD2
HD19
HD16
V
A11
A10
A9
A8
D29
D27
D24
GND
D20
D18
D13
D12
D10
D7
D5
D4
D1
D0
GND
VDDH
HD3
W
A6
A7
GND
GND
HD32
VDDH
HD33
VDDH
HD40
GND
VDDH
HDST0 HDST1
GND
VDDH
VDDH
GND
GND
HD4
HD5
HD6
Y
A5
A4
VDDH
HD34
HD37
GND
VDDH
GND
HD43
VDDH
GND
HD51
VDDH
GND
HD58
HD60
VDD
HD9
VDDH
HD15
HD7
AA
A3
A2
A0
HD35
HD38
HD42
GND
HD46
VDDH
GND
VDDH
HD52
HD54
VDDH
GND
HD59
HD63
HD10
HD12
HD14
VDD
AB
VDD
A1
HD36
HD39
HD41
HD44
HD45
HD47
HD48
HD49
HD50
HD53
HD55
HD56
HD57
HD61
HD62
HD8
HD11
HD13
GND
Figure 3-2. MSC8102 High Temperature Coefficient for Expansion Flip Chip Ceramic Ball Grid Array (High CTE FC-CBGA), Bottom View
3-3
FC-CBGA (HCTE) Package Description
Table 3-1. MSC8102 Signal Listing By Name
Signal Name
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 AACK ABB ALE
Location Designator
AA20 AB21 AA21 AA22 Y21 Y22 W22 W21 V19 V20 V21 V22 U21 U22 T22 T21 R22 R20 R21 P22 N22 M22 L22 N21 M21 L21 K20 L20 K22 K21 J22 H22 H12 G12 K17
3-4
FC-CBGA (HCTE) Package Description
Table 3-1. MSC8102 Signal Listing By Name (Continued)
Signal Name
ARTRY BADDR27 BADDR28 BADDR29 BADDR30 BADDR31 BCTL0 BCTL1 BG BNKSEL0 BNKSEL1 BNKSEL2 BM0 BM1 BM2 BR CHIP_ID0 CHIP_ID1 CHIP_ID2 CHIP_ID3 CLKIN CLKOUT CNFGS CS0 CS1 CS2 CS3 CS4 CS5 CS5 CS6 CS7 D0 D1 D2
Location Designator
H11 J8 L7 L8 K8 G10 G18 J18 N16 G11 H10 J11 G11 H10 J11 P16 B19 C18 C17 D17 J10 K14 W3 N18 G17 K18 L18 H17 K16 J18 J16 H16 V5 V6 U5
3-5
FC-CBGA (HCTE) Package Description
Table 3-1. MSC8102 Signal Listing By Name (Continued)
Signal Name
D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37
Location Designator
U6 V7 V8 U7 V9 U8 U9 V10 U10 V11 V12 U11 U12 T12 U13 V13 U14 V14 T14 U15 T15 V16 U16 U17 V17 U18 V18 T19 U19 W18 W16 Y19 AA19 AB20 Y18
3-6
FC-CBGA (HCTE) Package Description
Table 3-1. MSC8102 Signal Listing By Name (Continued)
Signal Name
D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 DACK1 DACK1 DACK2 DACK2 DACK3 DACK4 DBB DBG DLLIN
Location Designator
AA18 AB19 W14 AB18 AA17 Y14 AB17 AB16 AA15 AB15 AB14 AB13 AB12 Y11 AA11 AB11 AA10 AB10 AB9 AB8 Y8 AA7 Y7 AB7 AB6 AA6 G21 T18 F22 R19 T17 T16 H13 J12 K9
3-7
FC-CBGA (HCTE) Package Description
Table 3-1. MSC8102 Signal Listing By Name (Continued)
Signal Name
DONE1 DONE2 DP0 DP1 DP2 DP3 DP4 DP5 DP6 DP7 DRACK1 DRACK2 DREQ1 DREQ1 DREQ2 DREQ2 DREQ3 DREQ4 DSI64 DSISYNC EE0 EE1 EXT_BG2 EXT_BG3 EXT_BR2 EXT_BR3 EXT_DBG2 EXT_DBG3 GBL GND GND GND GND GND GND
Location Designator
F19 G22 P19 T18 R19 R17 T17 T16 R16 R15 F19 G22 G19 P19 F18 R17 R16 R15 U4 T4 D3 D4 T18 T16 P19 R17 R19 T17 R10 B4 B5 B7 B9 B11 B13
3-8
FC-CBGA (HCTE) Package Description
Table 3-1. MSC8102 Signal Listing By Name (Continued)
Signal Name
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
Location Designator
B15 B17 B22 C2 C8 C10 C12 C14 C15 D5 D9 D11 D13 D21 E8 E10 E12 E14 E15 E17 E18 F7 F11 F13 F15 G20 J6 J14 J20 K10 K11 K12 K13 K19 L9
3-9
FC-CBGA (HCTE) Package Description
Table 3-1. MSC8102 Signal Listing By Name (Continued)
Signal Name
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GNDSYN
Location Designator
L10 L14 L16 L17 M5 M6 M7 M10 M14 M19 N10 N14 P10 P13 P14 P21 R4 T20 V4 V15 W5 W6 W9 W13 W19 W20 Y9 Y12 Y15 Y17 AA8 AA13 AA16 AB2 P11
3-10
FC-CBGA (HCTE) Package Description
Table 3-1. MSC8102 Signal Listing By Name (Continued)
Signal Name
GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 GPIO22 GPIO23 GPIO24 GPIO25 GPIO26 GPIO27 GPIO28 GPIO29 GPIO30 GPIO31 HA11 HA12 HA13
Location Designator
B19 C18 C17 C20 D19 C21 C22 C19 D22 E19 E21 F20 E22 E20 F21 G19 F19 G21 F18 F22 F17 H19 G22 J19 H18 J21 N20 E6 C6 D17 C16 D16 L4 L2 J5
3-11
FC-CBGA (HCTE) Package Description
Table 3-1. MSC8102 Signal Listing By Name (Continued)
Signal Name
HA14 HA15 HA16 HA17 HA18 HA19 HA20 HA21 HA22 HA23 HA24 HA25 HA26 HA27 HA28 HA29 HBCS HBRST HCID0 HCID1 HCID2 HCID3 HCLKIN HCS HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7 HD8 HD9 HD10
Location Designator
L3 K2 K4 G6 J2 H5 H2 K3 F6 G5 G2 G4 J3 G3 H3 F5 N9 M16 E7 C7 D7 D8 P9 N17 T5 T4 U4 V2 W4 W3 W2 Y2 AB5 Y5 AA5
3-12
FC-CBGA (HCTE) Package Description
Table 3-1. MSC8102 Signal Listing By Name (Continued)
Signal Name
HD11 HD12 HD13 HD14 HD15 HD16 HD17 HD18 HD19 HD20 HD21 HD22 HD23 HD24 HD25 HD26 HD27 HD28 HD29 HD30 HD31 HD32 HD33 HD34 HD35 HD36 HD37 HD38 HD39 HD40 HD41 HD42 HD43 HD44 HD45
Location Designator
AB4 AA4 AB3 AA3 Y3 U2 T2 R2 U3 P2 T3 R5 P5 N5 P4 N2 P3 M2 N4 N3 M3 W18 W16 Y19 AA19 AB20 Y18 AA18 AB19 W14 AB18 AA17 Y14 AB17 AB16
3-13
FC-CBGA (HCTE) Package Description
Table 3-1. MSC8102 Signal Listing By Name (Continued)
Signal Name
HD46 HD47 HD48 HD49 HD50 HD51 HD52 HD53 HD54 HD55 HD56 HD57 HD58 HD59 HD60 HD61 HD62 HD63 HDBE4 HDBE5 HDBE6 HDBE7 HDBS4 HDBS5 HDBS6 HDBS7 HDST0 HDST1 HRDE HRDS HRESET HRW HTA HWBS0 HWBS1
Location Designator
AA15 AB15 AB14 AB13 AB12 Y11 AA11 AB11 AA10 AB10 AB9 AB8 Y8 AA7 Y7 AB7 AB6 AA6 R7 T7 R6 T6 R7 T7 R6 T6 W11 W10 N15 N15 E5 N15 H14 N8 P8
3-14
FC-CBGA (HCTE) Package Description
Table 3-1. MSC8102 Signal Listing By Name (Continued)
Signal Name
HWBS2 HWBS3 HWBS4 HWBS5 HWBS6 HWBS7 INT_OUT IRQ1 IRQ1 IRQ1 IRQ2 IRQ2 IRQ2 IRQ3 IRQ3 IRQ3 IRQ4 IRQ4 IRQ4 IRQ5 IRQ5 IRQ5 IRQ5 IRQ6 IRQ6 IRQ7 IRQ7 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14
Location Designator
P7 P6 R7 T7 R6 T6 G14 C20 R10 T18 D19 K8 R19 C21 G10 R17 C22 G12 T17 C19 H13 L8 T16 D22 R16 E19 G14 R15 E21 F20 E22 E20 F21 J19 H18
3-15
FC-CBGA (HCTE) Package Description
Table 3-1. MSC8102 Signal Listing By Name (Continued)
Signal Name
IRQ15 MODCK1 MODCK2 MWBE4 MWBE5 MWBE6 MWBE7 NMI NMI_OUT PBPL3 PBS0 PBS1 PBS2 PBS3 PBS4 PBS5 PBS6 PBS7 PGPL0 PGPL1 PGPL2 PGPL4 PGPL5 PGTA POE PORESET PPBS PSDA10 PSDAMUX PSDCAS PSDDQM0 PSDDQM1 PSDDQM2 PSDDQM3 PSDDQM4
Location Designator
J21 V2 W4 R7 T7 R6 T6 F4 B6 H7 G7 K6 N6 K5 R7 T7 R6 T6 J17 N19 K7 H8 J7 H8 K7 F2 H8 J17 J7 H7 G7 K6 N6 K5 R7
3-16
FC-CBGA (HCTE) Package Description
Table 3-1. MSC8102 Signal Listing By Name (Continued)
Signal Name
PSDDQM5 PSDDQM6 PSDDQM7 PSDRAS PSDVAL PSDWE PWE0 PWE1 PWE2 PWE3 PWE4 PWE5 PWE6 PWE7 PUPMWAIT RSTCONF SRESET SWTE TA TBST TC0 TC1 TC2 TCK TDI TDM0RCLK TDM0RDAT TDM0RSYN TDM0TCLK TDM0TDAT TDM0TSYN TDM1RCLK TDM1RDAT TDM1RSYN TDM1TCLK
Location Designator
T7 R6 T6 K7 P18 N19 G7 K6 N6 K5 R7 T7 R6 T6 H8 F3 C5 T5 P15 T10 G11 H10 J11 E2 D2 J21 N20 H18 G22 J19 H19 F22 F17 F18 F19
3-17
FC-CBGA (HCTE) Package Description
Table 3-1. MSC8102 Signal Listing By Name (Continued)
Signal Name
TDM1TDAT TDM1TSYN TDM2RCLK TDM2RDAT TDM2RSYN TDM2TCLK TDM2TDAT TDM2TSYN TDM3RCLK TDM3RDAT TDM3RSYN TDM3TCLK TDM3TDAT TDM3TSYN TDO TEA TEST TIMER0 TIMER1 TIMER2 TIMER3 TMCLK TMS TRST TS TSZ0 TSZ1 TSZ2 TSZ3 TT0 TT1 TT2 TT3 TT4 URXD
Location Designator
G21 G19 E20 F21 E22 E21 F20 E19 C19 D22 C22 D19 C21 C20 C4 P17 H6 C18 C17 C16 D16 C16 E4 E3 R18 T8 R8 T9 R9 R14 T13 K16 J16 H16 E6
3-18
FC-CBGA (HCTE) Package Description
Table 3-1. MSC8102 Signal Listing By Name (Continued)
Signal Name
UTXD VCCSYN VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
Location Designator
C6 P12 B8 B10 B12 B14 B16 B18 B20 B21 C3 C9 C11 C13 D10 D12 D14 D15 E9 E11 E13 E16 F8 F9 F10 F12 F14 F16 G8 G9 G13 G15 G16 H4 H9
3-19
FC-CBGA (HCTE) Package Description
Table 3-1. MSC8102 Signal Listing By Name (Continued)
Signal Name
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH
Location Designator
H15 H20 J4 J9 J13 J15 K15 M8 R11 R12 R13 T11 Y6 AA2 B3 AB22 D6 D18 D20 H21 L5 L6 L15 L19 M4 M9 M15 M17 M18 M20 N7 P20 R3 U20 V3
3-20
FC-CBGA (HCTE) Package Description
Table 3-1. MSC8102 Signal Listing By Name (Continued)
Signal Name
VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH
Location Designator
W7 W8 W12 W15 W17 Y4 Y10 Y13 Y16 Y20 AA9 AA12 AA14
Note: This table lists every signal name. Because many signals are multiplexed, an individual ball designator number may be listed several times.
Table 3-2. MSC8102 Signal Listing by Ball Designator
Number
B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17
Signal Name
VDD GND GND NMI_OUT GND VDD GND VDD GND VDD GND VDD GND VDD GND
3-21
FC-CBGA (HCTE) Package Description
Table 3-2. MSC8102 Signal Listing by Ball Designator (Continued)
Number
B18 B19 B20 B21 B22 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 D2 D3 D4 D5 D6 D7 D8 D9 D10
Signal Name
VDD GPIO0/CHIP_ID0 VDD VDD GND GND VDD TDO SRESET GPIO28/UTXD HCID1 GND VDD GND VDD GND VDD GND GND GPIO30/TIMER2/TMCLK GPIO2/TIMER1/CHIP_ID2 GPIO1/TIMER0/CHIP_ID1 GPIO7/TDM3RCLK/IRQ5 GPIO3/TDM3TSYN/IRQ1 GPIO5/TDM3TDAT/IRQ3 GPIO6/TDM3RSYN/IRQ4 TDI EE0 EE1 GND VDDH HCID2 HCID3 GND VDD
3-22
FC-CBGA (HCTE) Package Description
Table 3-2. MSC8102 Signal Listing by Ball Designator (Continued)
Number
D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 F2 F3
Signal Name
GND VDD GND VDD VDD GPIO31/TIMER3 GPIO29/CHIP_ID3 VDDH GPIO4/TDM3TCLK/IRQ2 VDDH GND GPIO8/TDM3RDAT/IRQ6 TCK TRST TMS HRESET GPIO27/URXD HCID0 GND VDD GND VDD GND VDD GND GND VDD GND GND GPIO9/TDM2TSYN/IRQ7 GPIO13/TDM2RCLK/IRQ11 GPIO10/TDM2TCLK/IRQ8 GPIO12/TDM2RSYN/IRQ10 PORESET RSTCONF
3-23
FC-CBGA (HCTE) Package Description
Table 3-2. MSC8102 Signal Listing by Ball Designator (Continued)
Number
F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17
Signal Name
NMI HA29 HA22 GND VDD VDD VDD GND VDD GND VDD GND VDD GPIO20/TDM1RDAT GPIO18/TDM1RSYN/DREQ2 GPIO16/TDM1TCLK/DONE1/DRACK1 GPIO11/TDM2TDAT/IRQ9 GPIO14/TDM2RDAT/IRQ12 GPIO19/TDM1RCLK/DACK2 HA24 HA27 HA25 HA23 HA17 PWE0/PSDDQM0/PBS0 VDD VDD IRQ3/BADDR31 BM0/TC0/BNKSEL0 ABB/IRQ4 VDD IRQ7/INT_OUT VDD VDD CS1
3-24
FC-CBGA (HCTE) Package Description
Table 3-2. MSC8102 Signal Listing by Ball Designator (Continued)
Number
G18 G19 G20 G21 G22 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 J2 J3 J4 J5 J6 J7 J8 J9 J10
Signal Name
BCTL0 GPIO15/TDM1TSYN/DREQ1 GND GPIO17/TDM1TDAT/DACK1 GPIO22/TDM0TCLK/DONE2/DRACK2 HA20 HA28 VDD HA19 TEST PSDCAS/PBPL3 PGTA/PUPMWAIT/PGPL4/PPBS VDD BM1/TC1/BNKSEL1 ARTRY AACK DBB/IRQ5 HTA VDD TT4/CS7 CS4 GPIO24/TDM0RSYN/IRQ14 GPIO21/TDM0TSYN VDD VDDH A31 HA18 HA26 VDD HA13 GND PSDAMUX/PGPL5 BADDR27 VDD CLKIN
3-25
FC-CBGA (HCTE) Package Description
Table 3-2. MSC8102 Signal Listing by Ball Designator (Continued)
Number
J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 L2 L3
Signal Name
BM2/TC2/BNKSEL2 DBG VDD GND VDD TT3/CS6 PSDA10/PGPL0 BCTL1/CS5 GPIO23/TDM0TDAT/IRQ13 GND GPIO25/TDM0RCLK/IRQ15 A30 HA15 HA21 HA16 PWE3/PSDDQM3/PBS3 PWE1/PSDDQM1/PBS1 POE/PSDRAS/PGPL2 IRQ2/BADDR30 DLLIN GND GND GND GND CLKOUT VDD TT2/CS5 ALE CS2 GND A26 A29 A28 HA12 HA14
3-26
FC-CBGA (HCTE) Package Description
Table 3-2. MSC8102 Signal Listing by Ball Designator (Continued)
Number
L4 L5 L6 L7 L8 L9 L10 L14 L15 L16 L17 L18 L19 L20 L21 L22 M2 M3 M4 M5 M6 M7 M8 M9 M10 M14 M15 M16 M17 M18 M19 M20 M21 M22 N2
Signal Name
HA11 VDDH VDDH BADDR28 IRQ5/BADDR29 GND GND GND VDDH GND GND CS3 VDDH A27 A25 A22 HD28 HD31 VDDH GND GND GND VDD VDDH GND GND VDDH HBRST VDDH VDDH GND VDDH A24 A21 HD26
3-27
FC-CBGA (HCTE) Package Description
Table 3-2. MSC8102 Signal Listing by Ball Designator (Continued)
Number
N3 N4 N5 N6 N7 N8 N9 N10 N14 N15 N16 N17 N18 N19 N20 N21 N22 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19
Signal Name
HD30 HD29 HD24 PWE2/PSDDQM2/PBS2 VDDH HWBS0 HBCS GND GND HRDS/HRW/HRDE BG HCS CS0 PSDWE/PGPL1 GPIO26/TDM0RDAT A23 A20 HD20 HD27 HD25 HD23 HWBS3 HWBS2 HWBS1 HCLKIN GND GNDSYN VCCSYN GND GND TA BR TEA PSDVAL DP0/DREQ1/EXT_BR2
3-28
FC-CBGA (HCTE) Package Description
Table 3-2. MSC8102 Signal Listing by Ball Designator (Continued)
Number
P20 P21 P22 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 T2 T3 T4 T5 T6 T7 T8 T9 T10
Signal Name
VDDH GND A19 HD18 VDDH GND HD22 HWBS6/HDBS6/MWBE6/HDBE6/PWE6/ PSDDQM6/PBS6 HWBS4/HDBS4/MWBE4/HDBE4/PWE4/ PSDDQM4/PBS4 TSZ1 TSZ3 IRQ1/GBL VDD VDD VDD TT0 IRQ7/DP7/DREQ4 IRQ6/DP6/DREQ3 IRQ3/DP3/DREQ2/EXT_BR3 TS IRQ2/DP2/DACK2/EXT_DBG2 A17 A18 A16 HD17 HD21 HD1/DSISYNC HD0/SWTE HWBS7/HDBS7/MWBE7/HDBE7/PWE7/ PSDDQM7/PBS7 HWBS5/HDBS5/MWBE5/HDBE5/PWE5/ PSDDQM5/PBS5 TSZ0 TSZ2 TBST
3-29
FC-CBGA (HCTE) Package Description
Table 3-2. MSC8102 Signal Listing by Ball Designator (Continued)
Number
T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 V2 V3
Signal Name
VDD D16 TT1 D21 D23 IRQ5/DP5/DACK4/EXT_BG3 IRQ4/DP4/DACK3/EXT_DBG3 IRQ1/DP1/DACK1/EXT_BG2 D30 GND A15 A14 HD16 HD19 HD2/DSI64 D2 D3 D6 D8 D9 D11 D14 D15 D17 D19 D22 D25 D26 D28 D31 VDDH A12 A13 HD3/MODCK1 VDDH
3-30
FC-CBGA (HCTE) Package Description
Table 3-2. MSC8102 Signal Listing by Ball Designator (Continued)
Number
V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17
Signal Name
GND D0 D1 D4 D5 D7 D10 D12 D13 D18 D20 GND D24 D27 D29 A8 A9 A10 A11 HD6 HD5/CNFGS HD4/MODCK2 GND GND VDDH VDDH GND HDST1 HDST0 VDDH GND HD40/D40 VDDH HD33/D33 VDDH
3-31
FC-CBGA (HCTE) Package Description
Table 3-2. MSC8102 Signal Listing by Ball Designator (Continued)
Number
W18 W19 W20 W21 W22 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10
Signal Name
HD32/D32 GND GND A7 A6 HD7 HD15 VDDH HD9 VDD HD60/D60 HD58/D58 GND VDDH HD51/D51 GND VDDH HD43/D43 GND VDDH GND HD37/D37 HD34/D34 VDDH A4 A5 VDD HD14 HD12 HD10 HD63/D63 HD59/D59 GND VDDH HD54/D54
3-32
FC-CBGA (HCTE) Package Description
Table 3-2. MSC8102 Signal Listing by Ball Designator (Continued)
Number
AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22
Signal Name
HD52/D52 VDDH GND VDDH HD46/D46 GND HD42/D42 HD38/D38 HD35/D35 A0 A2 A3 GND HD13 HD11 HD8 HD62/D62 HD61/D61 HD57/D57 HD56/D56 HD55/D55 HD53/D53 HD50/D50 HD49/D49 HD48/D48 HD47/D47 HD45/D45 HD44/D44 HD41/D41 HD39/D39 HD36/D36 A1 VDD
3-33
FC-CBGA (HCTE) Package Mechanical Drawing
3.3 FC-CBGA (HCTE) Package Mechanical Drawing
Notes: 1. All dimensions in millimeters. 2. Dimensioning and tolerancing per ASME Y14.5M-1994. 3. Maximum solder ball diameter measured parallel to Datum A. 4. Datum A, the seating plane, is determined by the spherical crowns of the solder balls.
CASE 1453-02
Figure 3-3. MSC8102 Mechanical Information, 431-pin FC-CBGA (HCTE) Package
3-34
FC-PBGA Package Mechanical Drawing
3.4 FC-PBGA Package Mechanical Drawing
Notes: 1. All dimensions in millimeters. 2. Dimensioning and tolerancing per ASME Y14.5, 1994. 3. Maximum solder ball diameter measured parallel to Datum A. 4. Datum A, the seating plane, is determined by the spherical crowns of the solder balls.
CASE 1385-01 Figure 3-4. MSC8102 Mechanical Information, 431-pin FC-PBGA Package Note: This package is used for pre-production MSC8102 devices only. The package may include a copper lid. Addition of the copper lid increases the overall package height to 2.58-3.22 mm, the same as the FC-CGBA (HCTE) package shown in Figure 3-3.
3-35
FC-PBGA Package Mechanical Drawing
3-36
Chapter 4
Design Considerations
4.1 Thermal Design Considerations
The average chip-junction temperature, TJ, in C can be obtained from the following:
Equation 1: TJ = TA + (PD *
where * * * * *
JA)
TA = ambient temperature C JA = package thermal resistance, junction to ambient, C/W PD = PINT + PI/O in W PINT = IDD x VDD in W--chip internal power PI/O = power dissipation on output pins in W--user determined
The user should set TA and PD such that TJ does not exceed the maximum operating conditions. In case TJ is too high, the user should either lower the ambient temperature or the power dissipation of the chip.
4.2 Power Supply Design Considerations
The input voltage must not exceed the I/O supply VDDH by more than 2.5 V at any time, including during power-on reset. In turn VDDH must not exceed VDD/V CCSYN by more than 2.6 V at any time, including during power-on reset. V DD/VCCSYN must not exceed VDDH by more than 0.4 V at any time, including during power-on reset. Therefore the recommendation is to use "bootstrap" diodes between the power rails, as shown in Figure 4-1.
I/O Power
MUR420 MUR420 MUR420
3.3 V (VDDH)
Core/PLL Supply
MUR420
1.6 V (VDD/VCCSYN)
Figure 4-1. Bootstrap Diodes for Power-Up Sequencing Select the bootstrap diodes such that a nominal V DD/VCCSYN is sourced from the V DDH power supply until the VDD/VCCSYN power supply becomes active. In Figure 4-1, four MUR420 Schottky barrier diodes are connected in series; each has a forward voltage (VF) of 0.6 V at high currents, so these diodes provide a 2.4 V drop, maintaining 0.9 V on the 1.6 V power line. Once the core/PLL power supply stabilizes at 1.6 V, the bootstrap diodes will be reverse biased with negligible leakage current. The V F should be effective at the current levels required by the processor. Do not use diodes with a nominal VF that drops too low at high current.
4-1
Connectivity Guidelines
Figure 4-2 shows the recommended power decoupling circuit for the core power supply. The voltage regulator and the decoupling capacitors should supply the required device current without any drop in voltage on the device pins. The voltage on the package pins should not drop below 1.5 V even for a very short spikes. This can be achieved by using the following guidelines: * For the core supply, use a voltage regulator rated at 1.6 V with nominal rating of at least 3 A. * Decouple the supply using low-ESR capacitors mounted as close as possible to the socket. Figure 4-2 shows three capacitors in parallel to reduce the resistance. Three capacitors is a recommended minimum number.
maximum IR drop of 15 mV at 1 A
Lmax = 2 cm
1.6 V
Power supply or Voltage Regulator
One 0.01 mF capacitor for every 3 Core supply pads.
MSC8102
(Imin = 3 A)
+ -
Bulk/Tantalum capacitors with low ESR and ESL Capacitors of 150 f
High Freq. capacitors (very low ESR and ESL)
Figure 4-2. Core Power Supply Decoupling
4.3 Connectivity Guidelines
Unused output pins can be disconnected, and unused input pins should be connected to there non-active value, except for the following: * If the DSI is unused (Bit DDR[1]:DSIDIS is set), then HCS and HBCS must be tied to VDD and all the rest of the DSI signals can be disconnected. * When the DSI uses Synchronous mode, HTA must be pulled up. In asynchronous mode, HTA should be pulled either up or down depending on design requirements. * HDST can be disconnected if the DSI is in Big-endian mode, or if the DSI is in Little-endian mode and DCR[7]:DSRFA bit is set. * When the DSI is in 64-bit Data bus mode and DCR[2]:BEM is cleared, the HWBS[1-3]/HDBS[1-3]/HWBE[1-3]/HDBE[1-3] and HWBS[4-7]/HDBS[4-7]/HWBE[4-7]/HDBE[4-7]/PWE[4-7]/PSDDQM[4-7]/PBS[4-7] must be tied to VDD. * When the DSI is in 32-bit Data bus mode and DCR[2] (BEM) is cleared, HWBS[1-3]/HDBS[1-3]/HWBE[1-3]/HDBE[1-3] must be tied to VDD. * When the DSI is in Asynchronous mode, HBRST and HCLKIN should either be disconnected or tied to VDD. * The following signals can be disconnected in single-master mode (BCR[EBM] is reset): BG, DBG, EXT_BG[2-3], EXT_DBG[2-3], GBL and TS. * The following signals must be pulled up: HRESET, SRESET, ARTRY, TA, TEA, PSDVAL, and AACK. 4-2
Power Considerations
* In single master mode, ABB and DBB can be selected as IRQ inputs and be connected to the non-active value. In other modes, they must be pulled up. * If the 60x-compatible system bus is not used and SIUMCR[PBSE] is set, PPBS can be disconnected. Otherwise, it should be pulled up. * The following signals: SWTE, DSISYNC, DSI64, MODCK[1-2], and CNFGS are used to configure the MSC8102 and are sampled on the deassertion of the PORESET signal. Therefore, they should be tied to GND or VDD either directly or through a pull-down or a pull-up resistor until the deassertion of the PORESET signal. * The following signals: CHIPID[0-3], RSTCONF and BM[0-2] are used to configure the MSC8102 and are sampled at the deassertion of the PORESET signal. Therefore, they should be tied to GND or VCC either directly or through a pull-down or a pull-up resistor. * The BR, BG, DBG, EXT_BR[2-3], EXT_BG[2-3], EXT_DBG[2-3], and TS must be pulled up if the BCR[EBM] bit is set. * When they are used, INT_OUT (if SIUMCR[INTODC] is cleared), NMI_OUT, and IRQxx (if not full drive) signals must be pulled up. Note: For details on configuration, see the MSC8102 User's Guide and MSC8102 Reference Manual.
4.4 Power Considerations
The internal power dissipation consists of three components: PINT = PTCORE + PSIU + PBUSES + PPERIPH The power dissipation depends on the operating frequency of the different portions of the chip. To determine the power dissipation at a given frequency, the following equations should be applied: PCORE (fc) = ((PCORE - PLCO)/275) x fc + PLCO PTCORE (fc) = (PCORE x 4) PSIU (fc) = ((PSIU - PLSI)/91.67) x fc + PLSI PPERIPH (fc) = ((PPERIPH - PLPE)/91.67) x fc + PLPE PBUSES (fc) = PBUSES /91.67 x fc Where, fc is the operating frequency in MHz and all power numbers are in mW PLCO is the SC140 Core leakage power PLSI is the SIU leakage power PLPE is the peripheral leakage power To determine a total power dissipation in a specific application, the following equation should be applied for each I/O output pin:
Equation 2: P = C x VDDH2 x fs x 10-3
Where: P = power in mW C = load capacitance in pF fs = output switching frequency in MHz.
4-3
Layout Practices
4.5 Layout Practices
Each VCC and VDD pin on the MSC8102 should be provided with a low-impedance path to the board power supply. Similarly, each GND pin should be provided with a low-impedance path to ground. The power supply pins drive distinct groups of logic on the chip. The VCC power supply should be bypassed to ground using at least four 0.1 F by-pass capacitors located as closely as possible to the four sides of the package. The capacitor leads and associated printed circuit traces connecting to chip VCC, VDD, and GND should be kept to less than half an inch per capacitor lead. A four-layer board is recommended, employing two inner layers as VCC and GND planes. All output pins on the MSC8102 have fast rise and fall times. Printed circuit board (PCB) trace interconnection length should be minimized in order to minimize undershoot and reflections caused by these fast output switching times. This recommendation particularly applies to the address and data busses. Maximum PCB trace lengths of six inches are recommended. Capacitance calculations should consider all device loads as well as parasitic capacitances due to the PCB traces. Attention to proper PCB layout and bypassing becomes especially critical in systems with higher capacitive loads because these loads create higher transient currents in the VCC, VDD, and GND circuits. Pull up all unused inputs or signals that will be inputs during reset. Special care should be taken to minimize the noise levels on the PLL supply pins. There is one pair of PLL supply pins: VCCSYN-GND SYN. To ensure internal clock stability, filter the power to the VCCSYN input with a circuit similar to the one in Figure 4-3. To filter as much noise as possible, place the circuit as close as possible to VCCSYN. The 0.01-F capacitor should be closest to VCCSYN, followed by the 10-F capacitor, the 10-nH inductor, and finally the 10- resistor to VDD. These traces should be kept short and direct.
GNDSYN should be provided with an extremely low impedance path to ground and should be bypassed to VCCSYN by a 0.01-F capacitor located as close as possible to the chip package. The user should also bypass GNDSYN to VCCSYN with a 0.01-F capacitor as close as possible to the chip package
VDD 10 10nH 10 F
VCCSYN
0.01 F
Figure 4-3. VCCSYN Bypass
4-4
Ordering Information
Consult a Motorola Semiconductor sales office or authorized distributor to determine product availability and place an order.
Core Frequency (MHz) 250 275
Part
Supply Voltage 1.6 V core 3.3 V I/O
Package Type
Pin Count 431
Order Number
MSC8102
High Temperature Coefficient for Expansion Flip Chip Ceramic Ball Grid Array (FC-CBGA (HCTE))
TBD TBD
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MSC8102/D, REV. 2

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